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authorSean Paul <seanpaul@chromium.org>2018-09-27 09:54:54 +0300
committerSean Paul <seanpaul@chromium.org>2018-09-27 09:54:54 +0300
commit7b76d0588477d4b6097a9048b42835a45caf5c48 (patch)
treefa4e0bcd49f8d17f26795224290c8f8460aa4116 /drivers/gpu/drm/bridge/thc63lvd1024.c
parenta74c0aa524050e5fd6c275a153b1f37283f6e37c (diff)
parentbf78296ab1cb215d0609ac6cff4e43e941e51265 (diff)
downloadlinux-7b76d0588477d4b6097a9048b42835a45caf5c48.tar.xz
Merge drm/drm-next into drm-misc-next
Backmerging 4.19-rc5 to pick up sun4i fix Signed-off-by: Sean Paul <seanpaul@chromium.org>
Diffstat (limited to 'drivers/gpu/drm/bridge/thc63lvd1024.c')
-rw-r--r--drivers/gpu/drm/bridge/thc63lvd1024.c18
1 files changed, 18 insertions, 0 deletions
diff --git a/drivers/gpu/drm/bridge/thc63lvd1024.c b/drivers/gpu/drm/bridge/thc63lvd1024.c
index c8b9edd5a7f4..b083a740565c 100644
--- a/drivers/gpu/drm/bridge/thc63lvd1024.c
+++ b/drivers/gpu/drm/bridge/thc63lvd1024.c
@@ -45,6 +45,23 @@ static int thc63_attach(struct drm_bridge *bridge)
return drm_bridge_attach(bridge->encoder, thc63->next, bridge);
}
+static enum drm_mode_status thc63_mode_valid(struct drm_bridge *bridge,
+ const struct drm_display_mode *mode)
+{
+ /*
+ * The THC63LVD1024 clock frequency range is 8 to 135 MHz in single-in
+ * mode. Note that the limits are different in dual-in, single-out mode,
+ * and will need to be adjusted accordingly.
+ */
+ if (mode->clock < 8000)
+ return MODE_CLOCK_LOW;
+
+ if (mode->clock > 135000)
+ return MODE_CLOCK_HIGH;
+
+ return MODE_OK;
+}
+
static void thc63_enable(struct drm_bridge *bridge)
{
struct thc63_dev *thc63 = to_thc63(bridge);
@@ -77,6 +94,7 @@ static void thc63_disable(struct drm_bridge *bridge)
static const struct drm_bridge_funcs thc63_bridge_func = {
.attach = thc63_attach,
+ .mode_valid = thc63_mode_valid,
.enable = thc63_enable,
.disable = thc63_disable,
};