diff options
| author | Kevin Wang <kevin1.wang@amd.com> | 2019-07-12 06:27:50 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-07-12 16:00:10 +0300 |
| commit | 64974ab24908a92b5dfe52e1ace3d67c47d657cb (patch) | |
| tree | 08d0d2567ead455be21e12bea8b23fb33037f75c /drivers/gpu/drm/amd/powerplay | |
| parent | d36893362d22ff46fdb105ebab12df00bbf23397 (diff) | |
| download | linux-64974ab24908a92b5dfe52e1ace3d67c47d657cb.tar.xz | |
drm/amd/powerplay: add pstate mclk(uclk) support for navi10
add pstate mclk(uclk) support.
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay')
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 8 |
2 files changed, 8 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c index c382eb901178..04132653e289 100644 --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c @@ -136,6 +136,7 @@ int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, return -EINVAL; switch (clk_type) { + case SMU_MCLK: case SMU_UCLK: if (!smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { pr_warn("uclk dpm is not enabled\n"); diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c index 4404528f969a..e25c1e3094ef 100644 --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c @@ -709,7 +709,7 @@ static int navi10_force_clk_levels(struct smu_context *smu, static int navi10_populate_umd_state_clk(struct smu_context *smu) { int ret = 0; - uint32_t min_sclk_freq = 0; + uint32_t min_sclk_freq = 0, min_mclk_freq = 0; ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL); if (ret) @@ -717,6 +717,12 @@ static int navi10_populate_umd_state_clk(struct smu_context *smu) smu->pstate_sclk = min_sclk_freq * 100; + ret = smu_get_dpm_freq_range(smu, SMU_MCLK, &min_mclk_freq, NULL); + if (ret) + return ret; + + smu->pstate_mclk = min_mclk_freq * 100; + return ret; } |