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authorHuang Rui <ray.huang@amd.com>2016-07-26 10:57:07 +0300
committerAlex Deucher <alexander.deucher@amd.com>2016-08-08 18:32:30 +0300
commite4e2c8f29a343953f0ff31bd2775b73cd8c07a4c (patch)
tree03657b2dbcce49e36256e899d39f6478b8fd1a54 /drivers/gpu/drm/amd/powerplay/hwmgr
parent9f7aab6fd396dcb7dacee152784ddf9c2f9b0e8b (diff)
downloadlinux-e4e2c8f29a343953f0ff31bd2775b73cd8c07a4c.tar.xz
drm/amd/powerplay: add deep sleep initialization
This patch adds the deep sleep initialization at DPM, it needs send a message to SMC to enable this feature before enable voltage controller. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/hwmgr')
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c34
1 files changed, 34 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c
index 7ffbbef60639..7a9749f48bca 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c
@@ -3069,6 +3069,36 @@ static int iceland_tf_start_smc(struct pp_hwmgr *hwmgr)
return ret;
}
+/**
+* Programs the Deep Sleep registers
+*
+* @param pHwMgr the address of the powerplay hardware manager.
+* @param pInput the pointer to input data (PhwEvergreen_DisplayConfiguration)
+* @param pOutput the pointer to output data (unused)
+* @param pStorage the pointer to temporary storage (unused)
+* @param Result the last failure code (unused)
+* @return always 0
+*/
+static int iceland_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
+{
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_SclkDeepSleep)) {
+ if (smum_send_msg_to_smc(hwmgr->smumgr,
+ PPSMC_MSG_MASTER_DeepSleep_ON) != 0)
+ PP_ASSERT_WITH_CODE(false,
+ "Attempt to enable Master Deep Sleep switch failed!",
+ return -EINVAL);
+ } else {
+ if (smum_send_msg_to_smc(hwmgr->smumgr,
+ PPSMC_MSG_MASTER_DeepSleep_OFF) != 0)
+ PP_ASSERT_WITH_CODE(false,
+ "Attempt to disable Master Deep Sleep switch failed!",
+ return -EINVAL);
+ }
+
+ return 0;
+}
+
static int iceland_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
{
int tmp_result, result = 0;
@@ -3133,6 +3163,10 @@ static int iceland_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
PP_ASSERT_WITH_CODE((0 == tmp_result),
"Failed to enable SCLK control!", return tmp_result);
+ tmp_result = iceland_enable_deep_sleep_master_switch(hwmgr);
+ PP_ASSERT_WITH_CODE((tmp_result == 0),
+ "Failed to enable deep sleep!", return tmp_result);
+
/* enable DPM */
tmp_result = iceland_start_dpm(hwmgr);
PP_ASSERT_WITH_CODE((0 == tmp_result),