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| author | Sunil Khatri <sunil.khatri@amd.com> | 2024-09-30 13:59:15 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2024-10-07 21:02:36 +0300 |
| commit | 82ae6619a450a53dd606d29df72f75d22d5d195a (patch) | |
| tree | a180909b2b5b554c79f730d780db9773ee4b9934 /drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | |
| parent | ded57e495158175c61f14662741ab4bd613c5bd0 (diff) | |
| download | linux-82ae6619a450a53dd606d29df72f75d22d5d195a.tar.xz | |
drm/amdgpu: update the handle ptr in wait_for_idle
Update the *handle to amdgpu_ip_block ptr for all
functions pointers of wait_for_idle.
Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c index 6c2acde977b8..7aeb59e5599f 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c @@ -1471,10 +1471,10 @@ static bool uvd_v7_0_is_idle(void *handle) return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); } -static int uvd_v7_0_wait_for_idle(void *handle) +static int uvd_v7_0_wait_for_idle(struct amdgpu_ip_block *ip_block) { unsigned i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; for (i = 0; i < adev->usec_timeout; i++) { if (uvd_v7_0_is_idle(handle)) @@ -1728,6 +1728,11 @@ static int uvd_v7_0_set_clockgating_state(void *handle, { struct amdgpu_device *adev = (struct amdgpu_device *)handle; bool enable = (state == AMD_CG_STATE_GATE); + struct amdgpu_ip_block *ip_block; + + ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD); + if (!ip_block) + return -EINVAL; uvd_v7_0_set_bypass_mode(adev, enable); @@ -1739,7 +1744,7 @@ static int uvd_v7_0_set_clockgating_state(void *handle, uvd_v7_0_set_sw_clock_gating(adev); } else { /* wait for STATUS to clear */ - if (uvd_v7_0_wait_for_idle(handle)) + if (uvd_v7_0_wait_for_idle(ip_block)) return -EBUSY; /* enable HW gates because UVD is idle */ |