diff options
| author | Yazen Ghannam <yazen.ghannam@amd.com> | 2023-01-27 20:04:06 +0300 |
|---|---|---|
| committer | Borislav Petkov (AMD) <bp@alien8.de> | 2023-03-24 15:03:19 +0300 |
| commit | 5a1adb375d7a86ee3b703f895b61de20773b6670 (patch) | |
| tree | 32b53f9f4edbd6a47c03f27ce59032d1210a5670 /drivers/edac | |
| parent | a2e59ab8e93301466cb3ff3f2b7b65eb1a4e8786 (diff) | |
| download | linux-5a1adb375d7a86ee3b703f895b61de20773b6670.tar.xz | |
EDAC/amd64: Do not discover ECC symbol size for Family 17h and later
The ECC symbol size was needed on legacy system to lookup the ECC syndrome.
This is not needed on modern systems because the ECC syndrome is explicitly
provided in the MCA information.
Remove the ECC symbol size discovery code for modern UMC-based systems.
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/r/20230127170419.1824692-10-yazen.ghannam@amd.com
Diffstat (limited to 'drivers/edac')
| -rw-r--r-- | drivers/edac/amd64_edac.c | 21 |
1 files changed, 3 insertions, 18 deletions
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 652ed7185659..bd0af17a318d 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1600,6 +1600,8 @@ static void __dump_misc_regs(struct amd64_pvt *pvt) debug_dump_dramcfg_low(pvt, pvt->dclr1, 1); edac_dbg(1, " DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no"); + + amd64_info("using x%u syndromes.\n", pvt->ecc_sym_sz); } /* Display and decode various NB registers for debug purposes. */ @@ -1609,8 +1611,6 @@ static void dump_misc_regs(struct amd64_pvt *pvt) __dump_misc_regs_df(pvt); else __dump_misc_regs(pvt); - - amd64_info("using x%u syndromes.\n", pvt->ecc_sym_sz); } /* @@ -3197,22 +3197,7 @@ static void determine_ecc_sym_sz(struct amd64_pvt *pvt) { pvt->ecc_sym_sz = 4; - if (pvt->umc) { - u8 i; - - for_each_umc(i) { - /* Check enabled channels only: */ - if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) { - if (pvt->umc[i].ecc_ctrl & BIT(9)) { - pvt->ecc_sym_sz = 16; - return; - } else if (pvt->umc[i].ecc_ctrl & BIT(7)) { - pvt->ecc_sym_sz = 8; - return; - } - } - } - } else if (pvt->fam >= 0x10) { + if (pvt->fam >= 0x10) { u32 tmp; amd64_read_pci_cfg(pvt->F3, EXT_NB_MCA_CFG, &tmp); |