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| author | Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> | 2019-09-26 13:50:57 +0300 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2019-10-15 13:11:55 +0300 |
| commit | 68fe2b520cee829ed518b4b1f64d2a557bcbffe1 (patch) | |
| tree | 6cbe57e6d548617343d316b84a45c1e5601c067b /drivers/dma | |
| parent | bd73dfabdda280fc5f05bdec79b6721b4b2f035f (diff) | |
| download | linux-68fe2b520cee829ed518b4b1f64d2a557bcbffe1.tar.xz | |
dmaengine: xilinx_dma: Fix 64-bit simple AXIDMA transfer
In AXI DMA simple mode also pass MSB bits of source and destination
address to xilinx_write function. It fixes simple AXI DMA operation
mode using 64-bit addressing.
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Link: https://lore.kernel.org/r/1569495060-18117-2-git-send-email-radhey.shyam.pandey@xilinx.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers/dma')
| -rw-r--r-- | drivers/dma/xilinx/xilinx_dma.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c index e7dc3c4dc8e0..1fbe0258578b 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -1354,7 +1354,8 @@ static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan) node); hw = &segment->hw; - xilinx_write(chan, XILINX_DMA_REG_SRCDSTADDR, hw->buf_addr); + xilinx_write(chan, XILINX_DMA_REG_SRCDSTADDR, + xilinx_prep_dma_addr_t(hw->buf_addr)); /* Start the transfer */ dma_ctrl_write(chan, XILINX_DMA_REG_BTT, |