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author | Russell King <rmk+kernel@arm.linux.org.uk> | 2013-11-06 21:15:16 +0400 |
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committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2014-04-04 03:30:18 +0400 |
commit | 59871902703c47acc730555be41bd9cb36d3700c (patch) | |
tree | dffebe3d0fdb69b7031be8eb8514a38954b297de /drivers/dma/omap-dma.c | |
parent | 965aeb4df1f2142f5a6407c6d40b7196be719582 (diff) | |
download | linux-59871902703c47acc730555be41bd9cb36d3700c.tar.xz |
dmaengine: omap-dma: move barrier to omap_dma_start_desc()
We don't need to issue a barrier for every segment of a DMA transfer;
doing this just once per descriptor will do.
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'drivers/dma/omap-dma.c')
-rw-r--r-- | drivers/dma/omap-dma.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c index 49609275b2e7..49b303296d75 100644 --- a/drivers/dma/omap-dma.c +++ b/drivers/dma/omap-dma.c @@ -195,7 +195,6 @@ static void omap_dma_start(struct omap_chan *c, struct omap_desc *d) val = c->plat->dma_read(CCR, c->dma_ch); val |= CCR_ENABLE; - mb(); c->plat->dma_write(val, CCR, c->dma_ch); } @@ -301,6 +300,13 @@ static void omap_dma_start_desc(struct omap_chan *c) c->desc = d = to_omap_dma_desc(&vd->tx); c->sgidx = 0; + /* + * This provides the necessary barrier to ensure data held in + * DMA coherent memory is visible to the DMA engine prior to + * the transfer starting. + */ + mb(); + c->plat->dma_write(d->ccr, CCR, c->dma_ch); if (dma_omap1()) c->plat->dma_write(d->ccr >> 16, CCR2, c->dma_ch); |