diff options
| author | Dave Jiang <dave.jiang@intel.com> | 2018-06-11 22:49:03 +0300 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2018-06-19 07:30:16 +0300 |
| commit | 4cb0e60112168594da2ac8a7752b0250c4387733 (patch) | |
| tree | 05c7b217c60a1e897b0c93f76605300704eedfb6 /drivers/dma/ioat | |
| parent | ce397d215ccd07b8ae3f71db689aedb85d56ab40 (diff) | |
| download | linux-4cb0e60112168594da2ac8a7752b0250c4387733.tar.xz | |
dmaengine: ioatdma: set the completion address register after channel reset
It seems that starting with Skylake Xeon, channel reset clears the
completion address register. Make sure the completion address register is
set again after reset.
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers/dma/ioat')
| -rw-r--r-- | drivers/dma/ioat/dma.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/dma/ioat/dma.c b/drivers/dma/ioat/dma.c index 8b5b23a8ace9..23fb2fa04000 100644 --- a/drivers/dma/ioat/dma.c +++ b/drivers/dma/ioat/dma.c @@ -688,6 +688,12 @@ static void ioat_restart_channel(struct ioatdma_chan *ioat_chan) { u64 phys_complete; + /* set the completion address register again */ + writel(lower_32_bits(ioat_chan->completion_dma), + ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_LOW); + writel(upper_32_bits(ioat_chan->completion_dma), + ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH); + ioat_quiesce(ioat_chan, 0); if (ioat_cleanup_preamble(ioat_chan, &phys_complete)) __cleanup(ioat_chan, phys_complete); |