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| author | Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2019-01-07 14:07:39 +0300 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2019-01-07 15:27:13 +0300 |
| commit | 91f0ff883e9ae654503fc62c588eefc8558e457f (patch) | |
| tree | 69eb9940144d3d6fd2e6066e81c636237e3171f1 /drivers/dma/dw/idma32.c | |
| parent | 69da8be90d5e85e60b5377c47384154b9dabf592 (diff) | |
| download | linux-91f0ff883e9ae654503fc62c588eefc8558e457f.tar.xz | |
dmaengine: dw: Reset DRAIN bit when resume the channel
For Intel iDMA 32-bit the channel can be drained on a suspend.
We need to reset the bit on the resume to return a status quo.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers/dma/dw/idma32.c')
| -rw-r--r-- | drivers/dma/dw/idma32.c | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/drivers/dma/dw/idma32.c b/drivers/dma/dw/idma32.c index 8707830f39ad..cd23b9238333 100644 --- a/drivers/dma/dw/idma32.c +++ b/drivers/dma/dw/idma32.c @@ -34,12 +34,20 @@ static void idma32_suspend_chan(struct dw_dma_chan *dwc, bool drain) if (drain) cfglo |= IDMA32C_CFGL_CH_DRAIN; - else - cfglo &= ~IDMA32C_CFGL_CH_DRAIN; channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP); } +static void idma32_resume_chan(struct dw_dma_chan *dwc, bool drain) +{ + u32 cfglo = channel_readl(dwc, CFG_LO); + + if (drain) + cfglo &= ~IDMA32C_CFGL_CH_DRAIN; + + channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP); +} + static u32 idma32_bytes2block(struct dw_dma_chan *dwc, size_t bytes, unsigned int width, size_t *len) { @@ -117,6 +125,7 @@ int idma32_dma_probe(struct dw_dma_chip *chip) /* Channel operations */ dw->initialize_chan = idma32_initialize_chan; dw->suspend_chan = idma32_suspend_chan; + dw->resume_chan = idma32_resume_chan; dw->encode_maxburst = idma32_encode_maxburst; dw->bytes2block = idma32_bytes2block; dw->block2bytes = idma32_block2bytes; |