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authorKai Ye <yekai13@huawei.com>2021-06-11 12:06:49 +0300
committerHerbert Xu <herbert@gondor.apana.org.au>2021-06-17 10:07:32 +0300
commitc02f5302e46a2505cb0a6170470759a7db929979 (patch)
tree3df2f5e2d676d648170fed573f6e097b30eac61c /drivers/crypto
parent3d2a429271bb622da48983631625c20de3b5f1e5 (diff)
downloadlinux-c02f5302e46a2505cb0a6170470759a7db929979.tar.xz
crypto: hisilicon/hpre - adds the max shaper type rate
The HPRE driver support configure each function's QoS in the Host for Kunpeng930. The HPRE driver needs to configure the maximum shaper type rate. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'drivers/crypto')
-rw-r--r--drivers/crypto/hisilicon/hpre/hpre_main.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/crypto/hisilicon/hpre/hpre_main.c b/drivers/crypto/hisilicon/hpre/hpre_main.c
index 37c529600847..8b0640fb04be 100644
--- a/drivers/crypto/hisilicon/hpre/hpre_main.c
+++ b/drivers/crypto/hisilicon/hpre/hpre_main.c
@@ -92,6 +92,7 @@
#define HPRE_QM_PM_FLR BIT(11)
#define HPRE_QM_SRIOV_FLR BIT(12)
+#define HPRE_SHAPER_TYPE_RATE 128
#define HPRE_VIA_MSI_DSM 1
#define HPRE_SQE_MASK_OFFSET 8
#define HPRE_SQE_MASK_LEN 24
@@ -947,6 +948,7 @@ static int hpre_pf_probe_init(struct hpre *hpre)
static int hpre_probe_init(struct hpre *hpre)
{
+ u32 type_rate = HPRE_SHAPER_TYPE_RATE;
struct hisi_qm *qm = &hpre->qm;
int ret;
@@ -954,6 +956,11 @@ static int hpre_probe_init(struct hpre *hpre)
ret = hpre_pf_probe_init(hpre);
if (ret)
return ret;
+ /* Enable shaper type 0 */
+ if (qm->ver >= QM_HW_V3) {
+ type_rate |= QM_SHAPER_ENABLE;
+ qm->type_rate = type_rate;
+ }
}
return 0;