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authorKonrad Dybcio <konrad.dybcio@linaro.org>2023-12-18 19:02:06 +0300
committerBjorn Andersson <andersson@kernel.org>2023-12-19 20:27:03 +0300
commit7e77a39265293ea4f05e20fff180755503c49918 (patch)
tree32f138d07f4fa29c8f9334832185364711d14e9d /drivers/clk
parente7fe73fc6b68ee97b1e8f124a66a5ee50d8d5e5b (diff)
downloadlinux-7e77a39265293ea4f05e20fff180755503c49918.tar.xz
clk: qcom: gcc-sm8550: use collapse-voting for PCIe GDSCs
The PCIe GDSCs can be shared with other masters and should use the APCS collapse-vote register when updating the power state. This is specifically also needed to be able to disable power domains that have been enabled by boot firmware using the vote register. Following other recent Qualcomm platforms, describe this register and the corresponding mask for the PCIe (and _phy) GDSCs. Fixes: 955f2ea3b9e9 ("clk: qcom: Add GCC driver for SM8550") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231218-topic-8550_fixes-v1-5-ce1272d77540@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/qcom/gcc-sm8550.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/clk/qcom/gcc-sm8550.c b/drivers/clk/qcom/gcc-sm8550.c
index a16d07426b71..73bda0d03aa7 100644
--- a/drivers/clk/qcom/gcc-sm8550.c
+++ b/drivers/clk/qcom/gcc-sm8550.c
@@ -2998,6 +2998,8 @@ static struct clk_branch gcc_video_axi1_clk = {
static struct gdsc pcie_0_gdsc = {
.gdscr = 0x6b004,
+ .collapse_ctrl = 0x52020,
+ .collapse_mask = BIT(0),
.pd = {
.name = "pcie_0_gdsc",
},
@@ -3007,6 +3009,8 @@ static struct gdsc pcie_0_gdsc = {
static struct gdsc pcie_0_phy_gdsc = {
.gdscr = 0x6c000,
+ .collapse_ctrl = 0x52020,
+ .collapse_mask = BIT(3),
.pd = {
.name = "pcie_0_phy_gdsc",
},
@@ -3016,6 +3020,8 @@ static struct gdsc pcie_0_phy_gdsc = {
static struct gdsc pcie_1_gdsc = {
.gdscr = 0x8d004,
+ .collapse_ctrl = 0x52020,
+ .collapse_mask = BIT(1),
.pd = {
.name = "pcie_1_gdsc",
},
@@ -3025,6 +3031,8 @@ static struct gdsc pcie_1_gdsc = {
static struct gdsc pcie_1_phy_gdsc = {
.gdscr = 0x8e000,
+ .collapse_ctrl = 0x52020,
+ .collapse_mask = BIT(4),
.pd = {
.name = "pcie_1_phy_gdsc",
},