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| author | Biju Das <biju.das@bp.renesas.com> | 2018-09-11 13:12:48 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2018-09-19 17:37:56 +0300 |
| commit | 6ff9cb53dabca55952ef66853ff145f7c424f6bd (patch) | |
| tree | 4cadf484b3add36ef9e36e17e663fbaca70cbb0a /drivers/clk | |
| parent | bbd71915ee9c56cc585c76b4b3aee791152ffbff (diff) | |
| download | linux-6ff9cb53dabca55952ef66853ff145f7c424f6bd.tar.xz | |
clk: renesas: Add r8a7744 CPG Core Clock Definitions
Add all RZ/G1N Clock Pulse Generator Core Clock Outputs, as listed in
Table 7.2b ("List of Clocks [RZ/G1M/N]") of the RZ/G1 Hardware User's
Manual.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk')
0 files changed, 0 insertions, 0 deletions