diff options
| author | Jerome Brunet <jbrunet@baylibre.com> | 2017-06-08 16:55:45 +0300 |
|---|---|---|
| committer | Jerome Brunet <jbrunet@baylibre.com> | 2017-06-16 21:51:42 +0300 |
| commit | 215c80a7d65312911ca7b08d42b05652e27eed5f (patch) | |
| tree | e014b96014a3343c6bd7b6c0d633cccbf9cbb860 /drivers/clk | |
| parent | 46460a6be9df17d112e2a275e26403c294865396 (diff) | |
| download | linux-215c80a7d65312911ca7b08d42b05652e27eed5f.tar.xz | |
clk: meson: gxbb: add all clk81 parents
Remove the FIXME on clk81 mux and add all the documented parents
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/meson/gxbb.c | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index 2919a0e044a5..f4117a368aa1 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -603,7 +603,11 @@ static struct meson_clk_mpll gxbb_mpll2 = { * coordinated clock rates feature */ -static u32 mux_table_clk81[] = { 6, 5, 7 }; +static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 }; +static const char * const clk81_parent_names[] = { + "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4", + "fclk_div3", "fclk_div5" +}; static struct clk_mux gxbb_mpeg_clk_sel = { .reg = (void *)HHI_MPEG_CLK_CNTL, @@ -616,13 +620,12 @@ static struct clk_mux gxbb_mpeg_clk_sel = { .name = "mpeg_clk_sel", .ops = &clk_mux_ro_ops, /* - * FIXME bits 14:12 selects from 8 possible parents: + * bits 14:12 selects from 8 possible parents: * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2, * fclk_div4, fclk_div3, fclk_div5 */ - .parent_names = (const char *[]){ "fclk_div3", "fclk_div4", - "fclk_div5" }, - .num_parents = 3, + .parent_names = clk81_parent_names, + .num_parents = ARRAY_SIZE(clk81_parent_names), .flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED), }, }; |