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| author | Stephen Boyd <sboyd@kernel.org> | 2021-02-17 01:09:12 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2021-02-17 01:09:12 +0300 |
| commit | 11f83102d8790eb8cee5e5757b53146660ae468b (patch) | |
| tree | b54dd1283c76a8e6c6e31138ad3d5fe63148ffde /drivers/clk | |
| parent | 242d8cf626877f5fa43d7d574fa39a6b4e9c74a9 (diff) | |
| parent | f3d661d6b4412c9d5f60d0566554fab83f9db381 (diff) | |
| parent | d9d4944d36e804b4cc1a513198e637b67aa93831 (diff) | |
| parent | 6286ce1e3ece54799f12775f8ce2a1cba9cbcfc5 (diff) | |
| parent | fa4dd53eeebf99808762029a2bf04533cc34c5f9 (diff) | |
| parent | ddddfafd94d83233ab28769b96b45f4ebbe21427 (diff) | |
| download | linux-11f83102d8790eb8cee5e5757b53146660ae468b.tar.xz | |
Merge branches 'clk-vc5', 'clk-silabs', 'clk-aspeed', 'clk-qoriq' and 'clk-rohm' into clk-next
- Support crystal load capacitance for Versaclock VC5
- Add a "skip recall" DT binding for Silicon Labs' si570 to avoid glitches at boot
* clk-vc5:
clk: vc5: Add support for optional load capacitance
dt-bindings: clk: versaclock5: Add optional load capacitance property
* clk-silabs:
clk: si570: Skip NVM to RAM recall operation if an optional property is set
dt-bindings: clock: si570: Add 'silabs,skip-recall' property
* clk-aspeed:
clk: aspeed: Fix APLL calculate formula from ast2600-A2
* clk-qoriq:
clk: qoriq: use macros to generate pll_mask
* clk-rohm:
clk: BD718x7: Do not depend on parent driver data