diff options
| author | jianlong.huang <jianlong.huang@starfivetech.com> | 2022-04-26 13:36:44 +0300 |
|---|---|---|
| committer | jianlong.huang <jianlong.huang@starfivetech.com> | 2022-04-26 13:36:44 +0300 |
| commit | 3addbc0ee49e4a7d841150d944b6a0984919cbeb (patch) | |
| tree | efeb682a70d4e9faf1465a3f9e128bdc3d1b6a1e /drivers/clk | |
| parent | fd6f56903b35318b2a1b79d14ad092a57d08149a (diff) | |
| download | linux-3addbc0ee49e4a7d841150d944b6a0984919cbeb.tar.xz | |
add timer device and modify timer clk config
Signed-off-by: jianlong.huang <jianlong.huang@starfivetech.com>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/starfive/clk-starfive-jh7100.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/clk/starfive/clk-starfive-jh7100.c b/drivers/clk/starfive/clk-starfive-jh7100.c index b0c1126c528e..7d61977bd366 100644 --- a/drivers/clk/starfive/clk-starfive-jh7100.c +++ b/drivers/clk/starfive/clk-starfive-jh7100.c @@ -254,13 +254,13 @@ static const struct jh7100_clk_data jh7100_clk_data[] __initconst = { JH7100_GDIV(JH7100_CLK_I2C3_CORE, "i2c3_core", 0, 63, JH7100_CLK_PERH0_SRC), JH7100_GATE(JH7100_CLK_WDTIMER_APB, "wdtimer_apb", 0, JH7100_CLK_APB2_BUS), JH7100_GDIV(JH7100_CLK_WDT_CORE, "wdt_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), - JH7100_GDIV(JH7100_CLK_TIMER0_CORE, "timer0_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), - JH7100_GDIV(JH7100_CLK_TIMER1_CORE, "timer1_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), - JH7100_GDIV(JH7100_CLK_TIMER2_CORE, "timer2_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), - JH7100_GDIV(JH7100_CLK_TIMER3_CORE, "timer3_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), - JH7100_GDIV(JH7100_CLK_TIMER4_CORE, "timer4_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), - JH7100_GDIV(JH7100_CLK_TIMER5_CORE, "timer5_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), - JH7100_GDIV(JH7100_CLK_TIMER6_CORE, "timer6_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), + JH7100_GDIV(JH7100_CLK_TIMER0_CORE, "timer0_coreclk", CLK_IGNORE_UNUSED, 63, JH7100_CLK_PERH0_SRC), + JH7100_GDIV(JH7100_CLK_TIMER1_CORE, "timer1_coreclk", CLK_IGNORE_UNUSED, 63, JH7100_CLK_PERH0_SRC), + JH7100_GDIV(JH7100_CLK_TIMER2_CORE, "timer2_coreclk", CLK_IGNORE_UNUSED, 63, JH7100_CLK_PERH0_SRC), + JH7100_GDIV(JH7100_CLK_TIMER3_CORE, "timer3_coreclk", CLK_IGNORE_UNUSED, 63, JH7100_CLK_PERH0_SRC), + JH7100_GDIV(JH7100_CLK_TIMER4_CORE, "timer4_coreclk", CLK_IGNORE_UNUSED, 63, JH7100_CLK_PERH0_SRC), + JH7100_GDIV(JH7100_CLK_TIMER5_CORE, "timer5_coreclk", CLK_IGNORE_UNUSED, 63, JH7100_CLK_PERH0_SRC), + JH7100_GDIV(JH7100_CLK_TIMER6_CORE, "timer6_coreclk", CLK_IGNORE_UNUSED, 63, JH7100_CLK_PERH0_SRC), JH7100_GATE(JH7100_CLK_VP6INTC_APB, "vp6intc_apb", 0, JH7100_CLK_APB2_BUS), JH7100_GATE(JH7100_CLK_PWM_APB, "pwm_apb", CLK_IGNORE_UNUSED, JH7100_CLK_APB2_BUS), JH7100_GATE(JH7100_CLK_MSI_APB, "msi_apb", 0, JH7100_CLK_APB2_BUS), |