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authorUlf Hansson <ulf.hansson@linaro.org>2012-09-24 18:43:19 +0400
committerMike Turquette <mturquette@linaro.org>2012-10-29 22:06:07 +0400
commit2f896ac0be9a0c7739033ef1f8821223f4a6a908 (patch)
tree7f16d4c23127ace1ce7f36c22335a766edc7f5d6 /drivers/clk/ux500
parentb0ea0fc753bfda1e9c20af403187758eb32052fd (diff)
downloadlinux-2f896ac0be9a0c7739033ef1f8821223f4a6a908.tar.xz
clk: ux500: Update sdmmc clock to 100MHz for u8500
For u8500 and using 100MHz as the frequency also requires the ape opp 100 voltage, thus use the prcmu_opp_volt_scalable clock type. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk/ux500')
-rw-r--r--drivers/clk/ux500/u8500_clk.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/clk/ux500/u8500_clk.c b/drivers/clk/ux500/u8500_clk.c
index ca4a25ed844c..7bebf1f62c65 100644
--- a/drivers/clk/ux500/u8500_clk.c
+++ b/drivers/clk/ux500/u8500_clk.c
@@ -170,10 +170,11 @@ void u8500_clk_init(void)
clk_register_clkdev(clk, NULL, "mtu0");
clk_register_clkdev(clk, NULL, "mtu1");
- clk = clk_reg_prcmu_gate("sdmmcclk", NULL, PRCMU_SDMMCCLK, CLK_IS_ROOT);
+ clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL, PRCMU_SDMMCCLK,
+ 100000000,
+ CLK_IS_ROOT|CLK_SET_RATE_GATE);
clk_register_clkdev(clk, NULL, "sdmmc");
-
clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk",
PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE);
clk_register_clkdev(clk, "dsihs2", "mcde");