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| author | Thierry Reding <treding@nvidia.com> | 2015-04-20 16:05:33 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2016-04-28 13:41:48 +0300 |
| commit | 98c4b3661b5aee0e583d17d6304f6489c0f41155 (patch) | |
| tree | cdbb55a6cfb2d18bade67ba8ad2e876bfd743f71 /drivers/clk/tegra/clk-id.h | |
| parent | 3d0f4e5f7a7c9ef2d8504f2b42f9c4d3233ba707 (diff) | |
| download | linux-98c4b3661b5aee0e583d17d6304f6489c0f41155.tar.xz | |
clk: tegra: Add dpaux1 clock
This clock is of the same type as dpaux and is added to feed into the
second DPAUX block used in conjunction with SOR1.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-id.h')
| -rw-r--r-- | drivers/clk/tegra/clk-id.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h index 62ea38187b71..fe6c6afcfa60 100644 --- a/drivers/clk/tegra/clk-id.h +++ b/drivers/clk/tegra/clk-id.h @@ -71,6 +71,7 @@ enum clk_id { tegra_clk_disp2_8, tegra_clk_dp2, tegra_clk_dpaux, + tegra_clk_dpaux1, tegra_clk_dsialp, tegra_clk_dsia_mux, tegra_clk_dsiblp, |