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authorPeter De-Schrijver <pdeschrijver@nvidia.com>2018-07-12 14:53:01 +0300
committerStephen Boyd <sboyd@kernel.org>2018-07-25 23:45:09 +0300
commit633e79650b4f0ed8cd26076a376b5372c413b0f8 (patch)
tree003efc93a2f1b3bd8091bf3579097acdca04c2a9 /drivers/clk/tegra/Makefile
parentcb3ac5947afb3bb7e2f89c1b59f61dcf3e115fe1 (diff)
downloadlinux-633e79650b4f0ed8cd26076a376b5372c413b0f8.tar.xz
clk: tegra: Add sdmmc mux divider clock
Add a clock type to model the sdmmc switch divider clocks which have paths to source clocks bypassing the divider (Low Jitter paths). These are handled by selecting the lj path when the divider is 1 (ie the rate is the parent rate), otherwise the normal path with divider will be selected. Otherwise this clock behaves as a normal peripheral clock. Signed-off-by: Peter De-Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/tegra/Makefile')
-rw-r--r--drivers/clk/tegra/Makefile1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile
index c77d072eb333..6507acc843c7 100644
--- a/drivers/clk/tegra/Makefile
+++ b/drivers/clk/tegra/Makefile
@@ -8,6 +8,7 @@ obj-y += clk-periph-fixed.o
obj-y += clk-periph-gate.o
obj-y += clk-pll.o
obj-y += clk-pll-out.o
+obj-y += clk-sdmmc-mux.o
obj-y += clk-super.o
obj-y += clk-tegra-audio.o
obj-y += clk-tegra-periph.o