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authorJonathan Liu <net147@gmail.com>2017-10-17 15:18:03 +0300
committerMaxime Ripard <maxime.ripard@free-electrons.com>2017-10-17 20:32:16 +0300
commit4328a2186e5120cfd34c4f04c6e4b7e74fb8b7b4 (patch)
tree7885268058f023d0dd84044ba2a047adb4245ca2 /drivers/clk/sunxi-ng
parent553c7d5ba2fe64cdbfcdf49560ef71ef79810f93 (diff)
downloadlinux-4328a2186e5120cfd34c4f04c6e4b7e74fb8b7b4.tar.xz
clk: sunxi-ng: sun4i: Export video PLLs
The video PLLs are used directly by the HDMI controller. Export them so that we can use them in our DT node. Signed-off-by: Jonathan Liu <net147@gmail.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'drivers/clk/sunxi-ng')
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun4i-a10.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/sunxi-ng/ccu-sun4i-a10.h b/drivers/clk/sunxi-ng/ccu-sun4i-a10.h
index c5947c7c050e..23c908ad509f 100644
--- a/drivers/clk/sunxi-ng/ccu-sun4i-a10.h
+++ b/drivers/clk/sunxi-ng/ccu-sun4i-a10.h
@@ -29,7 +29,7 @@
#define CLK_PLL_AUDIO_4X 6
#define CLK_PLL_AUDIO_8X 7
#define CLK_PLL_VIDEO0 8
-#define CLK_PLL_VIDEO0_2X 9
+/* The PLL_VIDEO0_2X clock is exported */
#define CLK_PLL_VE 10
#define CLK_PLL_DDR_BASE 11
#define CLK_PLL_DDR 12
@@ -38,7 +38,7 @@
#define CLK_PLL_PERIPH 15
#define CLK_PLL_PERIPH_SATA 16
#define CLK_PLL_VIDEO1 17
-#define CLK_PLL_VIDEO1_2X 18
+/* The PLL_VIDEO1_2X clock is exported */
#define CLK_PLL_GPU 19
/* The CPU clock is exported */