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authorMike Turquette <mturquette@linaro.org>2014-05-13 06:11:13 +0400
committerMike Turquette <mturquette@linaro.org>2014-05-13 06:11:13 +0400
commita854aea24c09599be75e1456f9cbe2ba78320a7b (patch)
tree32bfeb98769bad0ed797dc0a62839fb80dee054c /drivers/clk/socfpga/clk-gate.c
parentb4b3bfd0b319b206d4f2fe3380f3d7d594e6e414 (diff)
parent0691bb1b5a1865b3bbc9b7ce6e26eff546abb1cf (diff)
downloadlinux-a854aea24c09599be75e1456f9cbe2ba78320a7b.tar.xz
Merge tag 'socfpga-clk-update-for-v3.16' of git://git.rocketboards.org/linux-socfpga-next into clk-next-socfpga
Adds support getting the divider registers for the MAIN PLL that was once thought to be hidden.
Diffstat (limited to 'drivers/clk/socfpga/clk-gate.c')
-rw-r--r--drivers/clk/socfpga/clk-gate.c1
1 files changed, 0 insertions, 1 deletions
diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c
index 501d513bf890..dd3a78c64795 100644
--- a/drivers/clk/socfpga/clk-gate.c
+++ b/drivers/clk/socfpga/clk-gate.c
@@ -32,7 +32,6 @@
#define SOCFPGA_MMC_CLK "sdmmc_clk"
#define SOCFPGA_GPIO_DB_CLK_OFFSET 0xA8
-#define div_mask(width) ((1 << (width)) - 1)
#define streq(a, b) (strcmp((a), (b)) == 0)
#define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)