diff options
| author | Heiko Stuebner <heiko@sntech.de> | 2015-07-05 12:00:20 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2015-07-07 01:09:22 +0300 |
| commit | 3536c97a52db2848d13512878c65affd98fd29db (patch) | |
| tree | 13d610ff256af2048fba3c2a4db5168ee957300d /drivers/clk/rockchip/clk.h | |
| parent | 7c8f03d5f2fae4ce625cdf93d03368825846924f (diff) | |
| download | linux-3536c97a52db2848d13512878c65affd98fd29db.tar.xz | |
clk: rockchip: add rk3368 clock controller
Describe the clock tree and software resets of the rk3368 ARM64 SoC
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/rockchip/clk.h')
| -rw-r--r-- | drivers/clk/rockchip/clk.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index b72dad074a75..f506df85e543 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -57,6 +57,22 @@ #define RK3288_EMMC_CON0 0x218 #define RK3288_EMMC_CON1 0x21c +#define RK3368_PLL_CON(x) RK2928_PLL_CON(x) +#define RK3368_CLKSEL_CON(x) ((x) * 0x4 + 0x100) +#define RK3368_CLKGATE_CON(x) ((x) * 0x4 + 0x200) +#define RK3368_GLB_SRST_FST 0x280 +#define RK3368_GLB_SRST_SND 0x284 +#define RK3368_SOFTRST_CON(x) ((x) * 0x4 + 0x300) +#define RK3368_MISC_CON 0x380 +#define RK3368_SDMMC_CON0 0x400 +#define RK3368_SDMMC_CON1 0x404 +#define RK3368_SDIO0_CON0 0x408 +#define RK3368_SDIO0_CON1 0x40c +#define RK3368_SDIO1_CON0 0x410 +#define RK3368_SDIO1_CON1 0x414 +#define RK3368_EMMC_CON0 0x418 +#define RK3368_EMMC_CON1 0x41c + enum rockchip_pll_type { pll_rk3066, }; |