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authorHeiko Stuebner <heiko@sntech.de>2015-01-20 23:06:55 +0300
committerHeiko Stuebner <heiko@sntech.de>2015-01-22 17:42:24 +0300
commite142a4e91443d0fc2185c821626e66729f323d1c (patch)
treecb7d1babcb5475e0e0492efd9729872f616abde5 /drivers/clk/rockchip/clk-rk3288.c
parentcc6430689e54cab75de5682084c1f0984d31a98b (diff)
downloadlinux-e142a4e91443d0fc2185c821626e66729f323d1c.tar.xz
clk: rockchip: add a dummy clock for the watchdog pclk on rk3288
The pclk supplying the watchdog is controlled via the SGRF register area. Currently we don't have any clock-type handling external clock bits like this one. Additionally the SGRF isn't even writable in every boot mode. But still the clock control is available and in the future someone might want to use it. Therefore define a simple clock for the time being so that the watchdog driver can read its rate. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk/rockchip/clk-rk3288.c')
-rw-r--r--drivers/clk/rockchip/clk-rk3288.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index 8bcda8804b74..320b8f060751 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -880,6 +880,14 @@ static void __init rk3288_clk_init(struct device_node *np)
pr_warn("%s: could not register clock hclk_vcodec_pre: %ld\n",
__func__, PTR_ERR(clk));
+ /* Watchdog pclk is controlled by RK3288_SGRF_SOC_CON0[1]. */
+ clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_pd_alive", 0, 1, 1);
+ if (IS_ERR(clk))
+ pr_warn("%s: could not register clock pclk_wdt: %ld\n",
+ __func__, PTR_ERR(clk));
+ else
+ rockchip_clk_add_lookup(clk, PCLK_WDT);
+
rockchip_clk_register_plls(rk3288_pll_clks,
ARRAY_SIZE(rk3288_pll_clks),
RK3288_GRF_SOC_STATUS1);