diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-04-01 16:01:36 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-05-11 10:58:13 +0300 |
| commit | c9d1b58b272e272fc7121929e2d0e0755ea1656e (patch) | |
| tree | c2d97e9ce5f6e64e1d5234c2b651909010f3ead3 /drivers/clk/renesas | |
| parent | 23b04c84e201e82c1929144a2ce1442bd64e77f3 (diff) | |
| download | linux-c9d1b58b272e272fc7121929e2d0e0755ea1656e.tar.xz | |
clk: renesas: div6: Switch to .determine_rate()
As the .round_rate() callback returns a long clock rate, it cannot
return clock rates that do not fit in signed long, but do fit in
unsigned long. Hence switch the DIV6 clocks on SH/R-Mobile and R-Car
SoCs from the old .round_rate() callback to the newer .determine_rate()
callback, which does not suffer from this limitation.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/7fd8c45cd8bf5c6d928ca69c8b669be35b93de09.1617281699.git.geert+renesas@glider.be
Diffstat (limited to 'drivers/clk/renesas')
| -rw-r--r-- | drivers/clk/renesas/clk-div6.c | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/drivers/clk/renesas/clk-div6.c b/drivers/clk/renesas/clk-div6.c index 2920bec49bce..3af65ef5690e 100644 --- a/drivers/clk/renesas/clk-div6.c +++ b/drivers/clk/renesas/clk-div6.c @@ -100,12 +100,14 @@ static unsigned int cpg_div6_clock_calc_div(unsigned long rate, return clamp(div, 1U, 64U); } -static long cpg_div6_clock_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) +static int cpg_div6_clock_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { - unsigned int div = cpg_div6_clock_calc_div(rate, *parent_rate); + unsigned int div = cpg_div6_clock_calc_div(req->rate, + req->best_parent_rate); - return *parent_rate / div; + req->rate = req->best_parent_rate / div; + return 0; } static int cpg_div6_clock_set_rate(struct clk_hw *hw, unsigned long rate, @@ -166,7 +168,7 @@ static const struct clk_ops cpg_div6_clock_ops = { .get_parent = cpg_div6_clock_get_parent, .set_parent = cpg_div6_clock_set_parent, .recalc_rate = cpg_div6_clock_recalc_rate, - .round_rate = cpg_div6_clock_round_rate, + .determine_rate = cpg_div6_clock_determine_rate, .set_rate = cpg_div6_clock_set_rate, }; |