diff options
| author | Konrad Dybcio <konrad.dybcio@linaro.org> | 2023-12-18 19:02:09 +0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2024-01-26 02:35:38 +0300 |
| commit | a3fb4404e3d4f474ea862db874f5ab3a8ff50add (patch) | |
| tree | a676060f1cbff1fe00846ae772b6025b7fd7e856 /drivers/clk/qcom | |
| parent | 053f354733aa3211ac3d58f963f01a5bbefb5ae7 (diff) | |
| download | linux-a3fb4404e3d4f474ea862db874f5ab3a8ff50add.tar.xz | |
clk: qcom: dispcc-sm8550: Update disp PLL settings
[ Upstream commit febd251d8775c4fb6e4acd6b5d7b0ed707f4611f ]
The settings in the driver seem to have been taken from an older
release. Update them to match the latest values.
Fixes: 90114ca11476 ("clk: qcom: add SM8550 DISPCC driver")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231218-topic-8550_fixes-v1-8-ce1272d77540@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'drivers/clk/qcom')
| -rw-r--r-- | drivers/clk/qcom/dispcc-sm8550.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/clk/qcom/dispcc-sm8550.c b/drivers/clk/qcom/dispcc-sm8550.c index aefa19f3c2c5..0b8f0904b339 100644 --- a/drivers/clk/qcom/dispcc-sm8550.c +++ b/drivers/clk/qcom/dispcc-sm8550.c @@ -81,6 +81,10 @@ static const struct alpha_pll_config disp_cc_pll0_config = { .config_ctl_val = 0x20485699, .config_ctl_hi_val = 0x00182261, .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, .user_ctl_val = 0x00000000, .user_ctl_hi_val = 0x00000005, }; @@ -108,6 +112,10 @@ static const struct alpha_pll_config disp_cc_pll1_config = { .config_ctl_val = 0x20485699, .config_ctl_hi_val = 0x00182261, .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, .user_ctl_val = 0x00000000, .user_ctl_hi_val = 0x00000005, }; |