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| author | Stephen Boyd <sboyd@kernel.org> | 2018-06-04 22:34:51 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2018-06-04 22:34:51 +0300 |
| commit | 77122d6f7477899ba6d1b2d340956bd6fd9ee3b5 (patch) | |
| tree | 40911e85581bc92ba22408867531d7f7e3fcfa99 /drivers/clk/qcom/gdsc.h | |
| parent | 36851edd7ea96ac74266de27b2ff7870e14563c8 (diff) | |
| parent | a3dcdc7e5417a369f59214f67cd642c95017cf3b (diff) | |
| download | linux-77122d6f7477899ba6d1b2d340956bd6fd9ee3b5.tar.xz | |
Merge branch 'clk-qcom-sdm845' into clk-next
* clk-qcom-sdm845:
clk: qcom: Export clk_fabia_pll_configure()
clk: qcom: Add video clock controller driver for SDM845
dt-bindings: clock: Introduce QCOM Video clock bindings
clk: qcom: Add Global Clock controller (GCC) driver for SDM845
clk: qcom: Add DT bindings for SDM845 gcc clock controller
clk: qcom: Configure the RCGs to a safe source as needed
clk: qcom: Add support for BRANCH_HALT_SKIP flag for branch clocks
clk: qcom: Simplify gdsc status checking logic
clk: qcom: gdsc: Add support to poll CFG register to check GDSC state
clk: qcom: gdsc: Add support to poll for higher timeout value
clk: qcom: gdsc: Add support to reset AON and block reset logic
clk: qcom: Add support for controlling Fabia PLL
clk: qcom: Clear hardware clock control bit of RCG
Also fixup the Kconfig mess where SDM845 GCC has msm8998 in the
description and also the video Kconfig says things slightly differently
from the GCC one so just make it the same.
Diffstat (limited to 'drivers/clk/qcom/gdsc.h')
| -rw-r--r-- | drivers/clk/qcom/gdsc.h | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h index 7fd78cec7e5b..bd1f2c780d0a 100644 --- a/drivers/clk/qcom/gdsc.h +++ b/drivers/clk/qcom/gdsc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, The Linux Foundation. All rights reserved. + * Copyright (c) 2015, 2017-2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -53,7 +53,10 @@ struct gdsc { #define VOTABLE BIT(0) #define CLAMP_IO BIT(1) #define HW_CTRL BIT(2) -#define ALWAYS_ON BIT(3) +#define SW_RESET BIT(3) +#define AON_RESET BIT(4) +#define POLL_CFG_GDSCR BIT(5) +#define ALWAYS_ON BIT(6) struct reset_controller_dev *rcdev; unsigned int *resets; unsigned int reset_count; |