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| author | Leo Ruan <tingquan.ruan@cn.bosch.com> | 2022-02-07 18:14:11 +0300 |
|---|---|---|
| committer | Philipp Zabel <p.zabel@pengutronix.de> | 2022-04-04 10:37:42 +0300 |
| commit | 070a88fd4a03f921b73a2059e97d55faaa447dab (patch) | |
| tree | d89e0d42e1c9e530cb79f5d29d6b4a12f4da44b3 /drivers/clk/qcom/clk-pll.h | |
| parent | e8083acc3f8cc2097917018e947fd4c857f60454 (diff) | |
| download | linux-070a88fd4a03f921b73a2059e97d55faaa447dab.tar.xz | |
gpu: ipu-v3: Fix dev_dbg frequency output
This commit corrects the printing of the IPU clock error percentage if
it is between -0.1% to -0.9%. For example, if the pixel clock requested
is 27.2 MHz but only 27.0 MHz can be achieved the deviation is -0.8%.
But the fixed point math had a flaw and calculated error of 0.2%.
Before:
Clocks: IPU 270000000Hz DI 24716667Hz Needed 27200000Hz
IPU clock can give 27000000 with divider 10, error 0.2%
Want 27200000Hz IPU 270000000Hz DI 24716667Hz using IPU, 27000000Hz
After:
Clocks: IPU 270000000Hz DI 24716667Hz Needed 27200000Hz
IPU clock can give 27000000 with divider 10, error -0.8%
Want 27200000Hz IPU 270000000Hz DI 24716667Hz using IPU, 27000000Hz
Signed-off-by: Leo Ruan <tingquan.ruan@cn.bosch.com>
Signed-off-by: Mark Jonas <mark.jonas@de.bosch.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Link: https://lore.kernel.org/r/20220207151411.5009-1-mark.jonas@de.bosch.com
Diffstat (limited to 'drivers/clk/qcom/clk-pll.h')
0 files changed, 0 insertions, 0 deletions