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| author | Stephen Boyd <sboyd@kernel.org> | 2018-10-02 00:57:43 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2018-10-02 00:57:43 +0300 |
| commit | e15d598b5c6f61785c85f6c2db3f3cec4d33e6c9 (patch) | |
| tree | 77d847f9e300a112d543d25d9af1a02f0b1d7c2a /drivers/clk/mvebu | |
| parent | 5b394b2ddf0347bef56e50c69a58773c94343ff3 (diff) | |
| parent | 8b2a37870419f4aa6e6f837aa8ec627eae984010 (diff) | |
| download | linux-e15d598b5c6f61785c85f6c2db3f3cec4d33e6c9.tar.xz | |
Merge tag 'sunxi-clk-for-4.20' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner
Pull allwinner clock changes from Maxime Ripard:
Our usual set of changes for the Allwinner SoCs clock support.
The most notable changes are:
- A bunch of changes and fixes to support the A64 display engine
- Some fixes to support the A83t display engine
* tag 'sunxi-clk-for-4.20' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
dt-bindings: clock: sun50i-a64-ccu: Add PLL_VIDEO0 macro
clk: sunxi-ng: a64: Add max. rate constraint to video PLLs
clk: sunxi-ng: a64: Add minimal rate for video PLLs
clk: sunxi-ng: sun50i: h6: Add 2x fixed post-divider to MMC module clocks
clk: sunxi-ng: a83t: Add max. rate constraint to video PLLs
clk: sunxi-ng: nkmp: Add constraint for maximum rate
clk: sunxi-ng: r40: Add max. rate constraint to video PLLs
clk: sunxi-ng: h3/h5: Add max. rate constraint to pll-video
clk: sunxi-ng: Add maximum rate constraint to NM PLLs
clk: sunxi-ng: h6: fix PWM gate/reset offset
clk: sunxi-ng: h6: fix bus clocks' divider position
Diffstat (limited to 'drivers/clk/mvebu')
0 files changed, 0 insertions, 0 deletions