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| author | Xingyu Wu <xingyu.wu@starfivetech.com> | 2023-08-21 18:29:15 +0300 |
|---|---|---|
| committer | Hal Feng <hal.feng@starfivetech.com> | 2024-01-12 10:09:19 +0300 |
| commit | 0db35bf792c8f8c483930c064cbbd2db6703879f (patch) | |
| tree | e4cd7240f83489b91d19f99a556b94810a9ae905 /drivers/clk/microchip/clk-pic32mzda.c | |
| parent | 053e9d112865f5ea2e79f0100455584796219805 (diff) | |
| download | linux-0db35bf792c8f8c483930c064cbbd2db6703879f.tar.xz | |
clk: starfive: jh7110-sys: Fix lower rate of CPUfreq by setting PLL0 rate to 1.5GHz
CPUfreq supports 4 cpu frequency loads on 375/500/750/1500MHz.
But now PLL0 rate is 1GHz and the cpu frequency loads become
333/500/500/1000MHz in fact.
So PLL0 rate should be set to 1.5GHz. Change the parent of cpu_root clock
and the divider of cpu_core before the setting.
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
Fixes: e2c510d6d630 ("riscv: dts: starfive: Add cpu scaling for JH7110 SoC")
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Diffstat (limited to 'drivers/clk/microchip/clk-pic32mzda.c')
0 files changed, 0 insertions, 0 deletions