diff options
| author | Neil Armstrong <narmstrong@baylibre.com> | 2017-03-22 13:32:24 +0300 |
|---|---|---|
| committer | Kevin Hilman <khilman@baylibre.com> | 2017-04-04 22:05:13 +0300 |
| commit | e194401cf4d49e7fe2f8ec994130d59e94f09137 (patch) | |
| tree | e0d715e615342843d6e1da4d7f3c284659bdff09 /drivers/clk/meson | |
| parent | 45fcbec70c084631dc430810dad14a7ece5000b8 (diff) | |
| download | linux-e194401cf4d49e7fe2f8ec994130d59e94f09137.tar.xz | |
clk: meson-gxbb: Add GP0 PLL init parameters
Tha Amlogic GXBB SoC GP0 PLL needs some vendor provided parameters to be
initializated in the the GP0 control registers before configuring the rate
with the rate table provided parameters.
GXBB GP0 PLL tweaks are also selected to respect the vendor init procedure.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1490178747-14837-3-git-send-email-narmstrong@baylibre.com
Diffstat (limited to 'drivers/clk/meson')
| -rw-r--r-- | drivers/clk/meson/gxbb.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index d07dc2255faf..db95038e50c6 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -352,6 +352,13 @@ static struct meson_clk_pll gxbb_sys_pll = { }, }; +struct pll_params_table gxbb_gp0_params_table[] = { + PLL_PARAM(HHI_GP0_PLL_CNTL, 0x6a000228), + PLL_PARAM(HHI_GP0_PLL_CNTL2, 0x69c80000), + PLL_PARAM(HHI_GP0_PLL_CNTL3, 0x0a5590c4), + PLL_PARAM(HHI_GP0_PLL_CNTL4, 0x0000500d), +}; + static struct meson_clk_pll gxbb_gp0_pll = { .m = { .reg_off = HHI_GP0_PLL_CNTL, @@ -368,6 +375,12 @@ static struct meson_clk_pll gxbb_gp0_pll = { .shift = 16, .width = 2, }, + .params = { + .params_table = gxbb_gp0_params_table, + .params_count = ARRAY_SIZE(gxbb_gp0_params_table), + .no_init_reset = true, + .clear_reset_for_lock = true, + }, .rate_table = gp0_pll_rate_table, .rate_count = ARRAY_SIZE(gp0_pll_rate_table), .lock = &clk_lock, |