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| author | Chun-Jie Chen <chun-jie.chen@mediatek.com> | 2022-05-13 10:36:21 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2022-05-19 03:42:22 +0300 |
| commit | e1fd35f5cdffea714f7a285a1eb68863c72acb4e (patch) | |
| tree | a4f1f85a46641ecb19c2f4616f9eee87305c37d3 /drivers/clk/mediatek/clk-mt8167-aud.c | |
| parent | 544e9ec70f9335b07498319a2dacc6732a73850b (diff) | |
| download | linux-e1fd35f5cdffea714f7a285a1eb68863c72acb4e.tar.xz | |
clk: mediatek: use en_mask as a pure div_en_mask
We no longer allow en_mask to be a combination of
pll_en_bit and div_en_mask, so remove pll_en_bit(bit0)
from en_mask to make en_mask a pure en_mask that only
used for pll dividers.
This commit continues the work done in commit 7cc4e1bbe300
("clk: mediatek: Fix asymmetrical PLL enable and disable
control") and commit f384c44754b7 ("clk: mediatek:
Add configurable enable control to mtk_pll_data") to
clean up en_mask(bit0) default setting.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Mandy Liu <mandyjh.liu@mediatek.com>
Link: https://lore.kernel.org/r/20220513073621.12923-1-mandyjh.liu@mediatek.com
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/mediatek/clk-mt8167-aud.c')
0 files changed, 0 insertions, 0 deletions