diff options
| author | Garmin.Chang <Garmin.Chang@mediatek.com> | 2023-03-31 15:36:04 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2023-03-31 21:51:20 +0300 |
| commit | 28b2bc99fa76f9a8eaf22ee40fdc2a1e65fff81c (patch) | |
| tree | bf49a6b418ca0603c6bcad9070ffc1012be503af /drivers/clk/mediatek/Makefile | |
| parent | 1086a5310f9c9421398cd12c00f605866aad24a5 (diff) | |
| download | linux-28b2bc99fa76f9a8eaf22ee40fdc2a1e65fff81c.tar.xz | |
clk: mediatek: Add MT8188 apmixedsys clock support
Add MT8188 apmixedsys clock controller which provides Plls
generated from SoC 26m and ssusb clock gate control.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230331123621.16167-3-Garmin.Chang@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/mediatek/Makefile')
| -rw-r--r-- | drivers/clk/mediatek/Makefile | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index bcd3b8c465aa..41b1f5f2d5c3 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -100,6 +100,7 @@ obj-$(CONFIG_COMMON_CLK_MT8186_MMSYS) += clk-mt8186-mm.o obj-$(CONFIG_COMMON_CLK_MT8186_VDECSYS) += clk-mt8186-vdec.o obj-$(CONFIG_COMMON_CLK_MT8186_VENCSYS) += clk-mt8186-venc.o obj-$(CONFIG_COMMON_CLK_MT8186_WPESYS) += clk-mt8186-wpe.o +obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192-apmixedsys.o clk-mt8192.o obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o |