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| author | Sergej Sawazki <sergej@taudac.com> | 2017-11-03 21:34:28 +0300 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2017-11-03 21:46:40 +0300 |
| commit | 81b3cc55afc3cde54df98f93fbd4704fab7cc0e0 (patch) | |
| tree | 575e3406f099ea7d4636146d37e871c94e0af9fa /drivers/clk/ingenic/cgu.c | |
| parent | eaf8abcfb21ecb5f6460d0505b03da4c3b7eee98 (diff) | |
| download | linux-81b3cc55afc3cde54df98f93fbd4704fab7cc0e0.tar.xz | |
ASoC: wm8741: Fix setting BCLK and LRCLK polarity
After checking the code and the datasheet, it seems like we are handling
the clock inversion (SND_SOC_DAIFMT_NB_IF and SND_SOC_DAIFMT_IB_IF) not
correctly.
>From the datasheet (Table 58):
R5 Format Control, BITS[5:4], [BCP:LRP]:
(0) 00 = normal BCLK, normal LRCLK
(1) 01 = normal BCLK, inverted LRCLK <-- Fix this
(2) 10 = inverted BCLK, normal LRCLK
(3) 11 = inverted BCLK, inverted LRCLK <-- Fix this
Signed-off-by: Sergej Sawazki <sergej@taudac.com>
Acked-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/clk/ingenic/cgu.c')
0 files changed, 0 insertions, 0 deletions