diff options
| author | Peng Fan <peng.fan@nxp.com> | 2022-02-25 12:00:02 +0300 |
|---|---|---|
| committer | Abel Vesa <abel.vesa@nxp.com> | 2022-04-07 11:04:11 +0300 |
| commit | cdc86e473b353c8a026a337ee9fb9e1fbbe2276b (patch) | |
| tree | e2a1c0531c428e0ecfbeecb83d21c43389effc4b /drivers/clk/imx/clk-imx8mq.c | |
| parent | 3123109284176b1532874591f7c81f3837bbdc17 (diff) | |
| download | linux-cdc86e473b353c8a026a337ee9fb9e1fbbe2276b.tar.xz | |
clk: imx8mq: add 27m phy pll ref clock
According to pll documentation, the 3rd pll ref clock should be
hdmi phy 27m clock, not dummy clock.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/20220225090002.2497057-3-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Diffstat (limited to 'drivers/clk/imx/clk-imx8mq.c')
| -rw-r--r-- | drivers/clk/imx/clk-imx8mq.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c index 83cc2b1c3294..a9e69b6355ed 100644 --- a/drivers/clk/imx/clk-imx8mq.c +++ b/drivers/clk/imx/clk-imx8mq.c @@ -25,7 +25,7 @@ static u32 share_count_sai6; static u32 share_count_dcss; static u32 share_count_nand; -static const char * const pll_ref_sels[] = { "osc_25m", "osc_27m", "dummy", "dummy", }; +static const char * const pll_ref_sels[] = { "osc_25m", "osc_27m", "hdmi_phy_27m", "dummy", }; static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", }; static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", }; static const char * const vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", }; |