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author | Linus Torvalds <torvalds@linux-foundation.org> | 2015-11-05 23:59:36 +0300 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2015-11-05 23:59:36 +0300 |
commit | f66477a0aeb77f97a7de5f791700dadc42f3f792 (patch) | |
tree | 0a49febcf211c33948be618860eb3d545b7c6608 /drivers/clk/imx/clk-imx31.c | |
parent | 400c5bd5a5b1faf3089322ace58b974446a8ddc3 (diff) | |
parent | e5bf1991ea62b4f4fc906d0828f7eed988fc3835 (diff) | |
download | linux-f66477a0aeb77f97a7de5f791700dadc42f3f792.tar.xz |
Merge tag 'clk-for-linus-20151104' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"The majority of the changes are driver updates and new device support.
The core framework is mostly unchanged this time around, with only a
couple patches to expose a clk provider API and make getting clk
parent names from DT more robust.
Driver updates:
- Support for clock controllers found on Broadcom Northstar SoCs and
bcm2835 SoC
- Support for Allwinner audio clocks
- A few cleanup patches for Tegra drivers and support for the highest
DFLL frequencies on Tegra124
- Samsung exynos7 fixes and improvements
- i.Mx SoC updates to add a few missing clocks and keep debug uart
clocks on during kernel intialization
- Some mediatek cleanups and support for more subsystem clocks
- Support for msm8916 gpu/audio clocks and qcom's GDSC power domain
controllers
- A new driver for the Silabs si514 clock chip"
* tag 'clk-for-linus-20151104' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (143 commits)
clk: qcom: msm8960: Fix dsi1/2 halt bits
clk: lpc18xx-cgu: fix potential system hang when disabling unused clocks
clk: lpc18xx-ccu: fix potential system hang when disabling unused clocks
clk: Add clk_hw_is_enabled() for use by clk providers
clk: Add stubs for of_clk_*() APIs when CONFIG_OF=n
clk: versatile-icst: fix memory leak
clk: Remove clk_{register,unregister}_multiplier()
clk: iproc: define Broadcom NS2 iProc clock binding
clk: iproc: define Broadcom NSP iProc clock binding
clk: ns2: add clock support for Broadcom Northstar 2 SoC
clk: iproc: Separate status and control variables
clk: iproc: Split off dig_filter
clk: iproc: Add PLL base write function
clk: nsp: add clock support for Broadcom Northstar Plus SoC
clk: iproc: Add PWRCTRL support
clk: cygnus: Convert all macros to all caps
ARM: cygnus: fix link failures when CONFIG_COMMON_CLK_IPROC is disabled
clk: imx31: add missing of_node_put
clk: imx27: add missing of_node_put
clk: si5351: add missing of_node_put
...
Diffstat (limited to 'drivers/clk/imx/clk-imx31.c')
-rw-r--r-- | drivers/clk/imx/clk-imx31.c | 39 |
1 files changed, 31 insertions, 8 deletions
diff --git a/drivers/clk/imx/clk-imx31.c b/drivers/clk/imx/clk-imx31.c index 1f8383475bb3..6a964144a5b5 100644 --- a/drivers/clk/imx/clk-imx31.c +++ b/drivers/clk/imx/clk-imx31.c @@ -62,7 +62,17 @@ enum mx31_clks { static struct clk *clk[clk_max]; static struct clk_onecell_data clk_data; -int __init mx31_clocks_init(unsigned long fref) +static struct clk ** const uart_clks[] __initconst = { + &clk[ipg], + &clk[uart1_gate], + &clk[uart2_gate], + &clk[uart3_gate], + &clk[uart4_gate], + &clk[uart5_gate], + NULL +}; + +static void __init _mx31_clocks_init(unsigned long fref) { void __iomem *base; struct device_node *np; @@ -132,6 +142,12 @@ int __init mx31_clocks_init(unsigned long fref) imx_check_clocks(clk, ARRAY_SIZE(clk)); + clk_set_parent(clk[csi], clk[upll]); + clk_prepare_enable(clk[emi_gate]); + clk_prepare_enable(clk[iim_gate]); + mx31_revision(); + clk_disable_unprepare(clk[iim_gate]); + np = of_find_compatible_node(NULL, NULL, "fsl,imx31-ccm"); if (np) { @@ -139,6 +155,13 @@ int __init mx31_clocks_init(unsigned long fref) clk_data.clk_num = ARRAY_SIZE(clk); of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); } +} + +int __init mx31_clocks_init(void) +{ + u32 fref = 26000000; /* default */ + + _mx31_clocks_init(fref); clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0"); clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0"); @@ -194,12 +217,8 @@ int __init mx31_clocks_init(unsigned long fref) clk_register_clkdev(clk[sdma_gate], NULL, "imx31-sdma"); clk_register_clkdev(clk[iim_gate], "iim", NULL); - clk_set_parent(clk[csi], clk[upll]); - clk_prepare_enable(clk[emi_gate]); - clk_prepare_enable(clk[iim_gate]); - mx31_revision(); - clk_disable_unprepare(clk[iim_gate]); + imx_register_uart_clocks(uart_clks); mxc_timer_init(MX31_GPT1_BASE_ADDR, MX31_INT_GPT, GPT_TYPE_IMX31); return 0; @@ -214,9 +233,13 @@ int __init mx31_clocks_init_dt(void) if (!of_device_is_compatible(np, "fsl,imx-osc26m")) continue; - if (!of_property_read_u32(np, "clock-frequency", &fref)) + if (!of_property_read_u32(np, "clock-frequency", &fref)) { + of_node_put(np); break; + } } - return mx31_clocks_init(fref); + _mx31_clocks_init(fref); + + return 0; } |