diff options
| author | Lars-Peter Clausen <lars@metafoo.de> | 2023-01-15 02:34:59 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2023-01-18 21:49:52 +0300 |
| commit | 4411da3209298b4ababc7d12940339c664e8db4a (patch) | |
| tree | d3a9425baa8006840b918303556472933f487bcb /drivers/clk/clk-versaclock5.c | |
| parent | 3ed741db04f58e8df0d46cec7ecfc4bfd075f047 (diff) | |
| download | linux-4411da3209298b4ababc7d12940339c664e8db4a.tar.xz | |
clk: vc5: Add support for 5P49V60
The 5P49V60 is very similar to the existing supported clock chips of the
versaclock5 driver and uses the same register map layout. But its maximum
VCO frequency is 2.7 GHz instead of 3 GHz for the other supported devices.
Add a vco_max field to the chip info field to allow to specify a per device
variant maximum VCO frequency.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Link: https://lore.kernel.org/r/20230114233500.3294789-2-lars@metafoo.de
Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/clk-versaclock5.c')
| -rw-r--r-- | drivers/clk/clk-versaclock5.c | 25 |
1 files changed, 22 insertions, 3 deletions
diff --git a/drivers/clk/clk-versaclock5.c b/drivers/clk/clk-versaclock5.c index 54fee43d6564..fa71a57875ce 100644 --- a/drivers/clk/clk-versaclock5.c +++ b/drivers/clk/clk-versaclock5.c @@ -122,9 +122,8 @@ #define VC5_GLOBAL_REGISTER 0x76 #define VC5_GLOBAL_REGISTER_GLOBAL_RESET BIT(5) -/* PLL/VCO runs between 2.5 GHz and 3.0 GHz */ +/* The minimum VCO frequency is 2.5 GHz. The maximum is variant specific. */ #define VC5_PLL_VCO_MIN 2500000000UL -#define VC5_PLL_VCO_MAX 3000000000UL /* VC5 Input mux settings */ #define VC5_MUX_IN_XIN BIT(0) @@ -150,6 +149,7 @@ enum vc5_model { IDT_VC5_5P49V5925, IDT_VC5_5P49V5933, IDT_VC5_5P49V5935, + IDT_VC6_5P49V60, IDT_VC6_5P49V6901, IDT_VC6_5P49V6965, IDT_VC6_5P49V6975, @@ -161,6 +161,7 @@ struct vc5_chip_info { const unsigned int clk_fod_cnt; const unsigned int clk_out_cnt; const u32 flags; + const unsigned long vco_max; }; struct vc5_driver_data; @@ -446,10 +447,11 @@ static long vc5_pll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw); + struct vc5_driver_data *vc5 = hwdata->vc5; u32 div_int; u64 div_frc; - rate = clamp(rate, VC5_PLL_VCO_MIN, VC5_PLL_VCO_MAX); + rate = clamp(rate, VC5_PLL_VCO_MIN, vc5->chip_info->vco_max); /* Determine integer part, which is 12 bit wide */ div_int = rate / *parent_rate; @@ -1209,6 +1211,7 @@ static const struct vc5_chip_info idt_5p49v5923_info = { .clk_fod_cnt = 2, .clk_out_cnt = 3, .flags = 0, + .vco_max = 3000000000UL, }; static const struct vc5_chip_info idt_5p49v5925_info = { @@ -1216,6 +1219,7 @@ static const struct vc5_chip_info idt_5p49v5925_info = { .clk_fod_cnt = 4, .clk_out_cnt = 5, .flags = 0, + .vco_max = 3000000000UL, }; static const struct vc5_chip_info idt_5p49v5933_info = { @@ -1223,6 +1227,7 @@ static const struct vc5_chip_info idt_5p49v5933_info = { .clk_fod_cnt = 2, .clk_out_cnt = 3, .flags = VC5_HAS_INTERNAL_XTAL, + .vco_max = 3000000000UL, }; static const struct vc5_chip_info idt_5p49v5935_info = { @@ -1230,6 +1235,15 @@ static const struct vc5_chip_info idt_5p49v5935_info = { .clk_fod_cnt = 4, .clk_out_cnt = 5, .flags = VC5_HAS_INTERNAL_XTAL, + .vco_max = 3000000000UL, +}; + +static const struct vc5_chip_info idt_5p49v60_info = { + .model = IDT_VC6_5P49V60, + .clk_fod_cnt = 4, + .clk_out_cnt = 5, + .flags = VC5_HAS_PFD_FREQ_DBL | VC5_HAS_BYPASS_SYNC_BIT, + .vco_max = 2700000000UL, }; static const struct vc5_chip_info idt_5p49v6901_info = { @@ -1237,6 +1251,7 @@ static const struct vc5_chip_info idt_5p49v6901_info = { .clk_fod_cnt = 4, .clk_out_cnt = 5, .flags = VC5_HAS_PFD_FREQ_DBL | VC5_HAS_BYPASS_SYNC_BIT, + .vco_max = 3000000000UL, }; static const struct vc5_chip_info idt_5p49v6965_info = { @@ -1244,6 +1259,7 @@ static const struct vc5_chip_info idt_5p49v6965_info = { .clk_fod_cnt = 4, .clk_out_cnt = 5, .flags = VC5_HAS_BYPASS_SYNC_BIT, + .vco_max = 3000000000UL, }; static const struct vc5_chip_info idt_5p49v6975_info = { @@ -1251,6 +1267,7 @@ static const struct vc5_chip_info idt_5p49v6975_info = { .clk_fod_cnt = 4, .clk_out_cnt = 5, .flags = VC5_HAS_BYPASS_SYNC_BIT | VC5_HAS_INTERNAL_XTAL, + .vco_max = 3000000000UL, }; static const struct i2c_device_id vc5_id[] = { @@ -1258,6 +1275,7 @@ static const struct i2c_device_id vc5_id[] = { { "5p49v5925", .driver_data = IDT_VC5_5P49V5925 }, { "5p49v5933", .driver_data = IDT_VC5_5P49V5933 }, { "5p49v5935", .driver_data = IDT_VC5_5P49V5935 }, + { "5p49v60", .driver_data = IDT_VC6_5P49V60 }, { "5p49v6901", .driver_data = IDT_VC6_5P49V6901 }, { "5p49v6965", .driver_data = IDT_VC6_5P49V6965 }, { "5p49v6975", .driver_data = IDT_VC6_5P49V6975 }, @@ -1270,6 +1288,7 @@ static const struct of_device_id clk_vc5_of_match[] = { { .compatible = "idt,5p49v5925", .data = &idt_5p49v5925_info }, { .compatible = "idt,5p49v5933", .data = &idt_5p49v5933_info }, { .compatible = "idt,5p49v5935", .data = &idt_5p49v5935_info }, + { .compatible = "idt,5p49v60", .data = &idt_5p49v60_info }, { .compatible = "idt,5p49v6901", .data = &idt_5p49v6901_info }, { .compatible = "idt,5p49v6965", .data = &idt_5p49v6965_info }, { .compatible = "idt,5p49v6975", .data = &idt_5p49v6975_info }, |