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authorKuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>2020-03-24 03:26:06 +0300
committerBjorn Helgaas <bhelgaas@google.com>2020-03-28 21:19:03 +0300
commitaea47413e7ceec6024f5a2b743cb1a4b2176bf3f (patch)
tree0512567689d5eae8e17a933578d0508214436aba /drivers/acpi/pci_root.c
parent20e15e673b05a045fdbe534d40edf948e1b0b1af (diff)
downloadlinux-aea47413e7ceec6024f5a2b743cb1a4b2176bf3f.tar.xz
PCI/DPC: Expose dpc_process_error(), dpc_reset_link() for use by EDR
If firmware controls DPC, it is generally responsible for managing the DPC capability and events, and the OS should not access the DPC capability. However, if firmware controls DPC and both the OS and the platform support Error Disconnect Recover (EDR) notifications, the OS EDR notify handler is responsible for recovery, and the notify handler may read/write the DPC capability until it clears the DPC Trigger Status bit. See [1], sec 4.5.1, table 4-6. Expose some DPC error handling functions so they can be used by the EDR notify handler. [1] Downstream Port Containment Related Enhancements ECN, Jan 28, 2019, affecting PCI Firmware Specification, Rev. 3.2 https://members.pcisig.com/wg/PCI-SIG/document/12888 Link: https://lore.kernel.org/r/e9000bb15b3a4293e81d98bb29ead7c84a6393c9.1585000084.git.sathyanarayanan.kuppuswamy@linux.intel.com Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'drivers/acpi/pci_root.c')
0 files changed, 0 insertions, 0 deletions