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authorMichael Chan <michael.chan@broadcom.com>2018-12-09 15:01:00 +0300
committerDavid S. Miller <davem@davemloft.net>2018-12-09 22:46:58 +0300
commit75720e6323a1d195ae3ebf1a7b5e17c2e687f552 (patch)
tree6eda592fd7ef4cc038c0902364de571b7abf9342 /crypto/deflate.c
parent804fba4e9f508c8004a4bfbdf3f300ca237c56df (diff)
downloadlinux-75720e6323a1d195ae3ebf1a7b5e17c2e687f552.tar.xz
bnxt_en: Keep track of reserved IRQs.
The new 57500 chips use 1 NQ per MSIX vector, whereas legacy chips use 1 CP ring per MSIX vector. To better unify this, add a resv_irqs field to struct bnxt_hw_resc. On legacy chips, we initialize resv_irqs with resv_cp_rings. On new chips, we initialize it with the allocated MSIX resources. Signed-off-by: Michael Chan <michael.chan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'crypto/deflate.c')
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