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| author | Russell King <rmk+kernel@armlinux.org.uk> | 2017-11-27 14:22:42 +0300 |
|---|---|---|
| committer | Russell King <rmk+kernel@armlinux.org.uk> | 2017-11-27 14:22:42 +0300 |
| commit | 3aaf33bebda8d4ffcc0fc8ef39e6c1ac68823b11 (patch) | |
| tree | cea1260797f0c3af391c048a53f46db026221f87 /block/bounce.c | |
| parent | 8bafae202c82dc257f649ea3c275a0f35ee15113 (diff) | |
| download | linux-3aaf33bebda8d4ffcc0fc8ef39e6c1ac68823b11.tar.xz | |
ARM: avoid faulting on qemu
When qemu starts a kernel in a bare environment, the default SCR has
the AW and FW bits clear, which means that the kernel can't modify
the PSR A or PSR F bits, and means that FIQs and imprecise aborts are
always masked.
When running uboot under qemu, the AW and FW SCR bits are set, and the
kernel functions normally - and this is how real hardware behaves.
Fix this for qemu by ignoring the FIQ bit.
Fixes: 8bafae202c82 ("ARM: BUG if jumping to usermode address in kernel mode")
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Diffstat (limited to 'block/bounce.c')
0 files changed, 0 insertions, 0 deletions