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authorGeert Uytterhoeven <geert@linux-m68k.org>2021-11-25 16:21:18 +0300
committerEmil Renner Berthing <kernel@esmil.dk>2022-07-13 00:19:07 +0300
commitf764bfb01fe417677aa7aaacfd2e67778d9e9eab (patch)
treecfcdc5068598e22cc1fb4f3ff51a13ef871099d9 /arch
parent42cec41743aebb3ea078e4c476f670bbc8294c46 (diff)
downloadlinux-f764bfb01fe417677aa7aaacfd2e67778d9e9eab.tar.xz
riscv: dts: starfive: Group tuples in interrupt properties
To improve human readability and enable automatic validation, the tuples in the various properties containing interrupt specifiers should be grouped. Fix this by grouping the tuples of "interrupts-extended" properties using angle brackets. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/riscv/boot/dts/starfive/jh7100.dtsi8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
index 69f22f9aad9d..d74fc29af642 100644
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
@@ -106,15 +106,15 @@
clint: clint@2000000 {
compatible = "starfive,jh7100-clint", "sifive,clint0";
reg = <0x0 0x2000000 0x0 0x10000>;
- interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
- &cpu1_intc 3 &cpu1_intc 7>;
+ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+ <&cpu1_intc 3>, <&cpu1_intc 7>;
};
plic: interrupt-controller@c000000 {
compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0";
reg = <0x0 0xc000000 0x0 0x4000000>;
- interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9
- &cpu1_intc 11 &cpu1_intc 9>;
+ interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
+ <&cpu1_intc 11>, <&cpu1_intc 9>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;