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| author | Andy Hu <andy.hu@starfivetech.com> | 2023-08-31 05:06:00 +0300 |
|---|---|---|
| committer | Andy Hu <andy.hu@starfivetech.com> | 2023-08-31 05:06:00 +0300 |
| commit | c698aee1b2dc0772f4a8ea5f2777b9e5710630d2 (patch) | |
| tree | 076e91dc5144cc79f24696064026ac844e1449c9 /arch | |
| parent | 05533e9c31d6f0da20efc2d436a3b0f6d516ed4b (diff) | |
| parent | 45c6eeaad9c30b4b558b1ad8380332eb257b4884 (diff) | |
| download | linux-c698aee1b2dc0772f4a8ea5f2777b9e5710630d2.tar.xz | |
Merge tag 'JH7110_515_SDK_v5.7.0' into vf2-515-devel
Diffstat (limited to 'arch')
| -rw-r--r--[-rwxr-xr-x] | arch/riscv/boot/dts/starfive/jh7110.dtsi | 23 |
1 files changed, 12 insertions, 11 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 1998e00fe8de..a2831f719bca 100755..100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -629,7 +629,7 @@ }; dma: dma-controller@16050000 { - compatible = "starfive,jh7110-dma", "snps,axi-dma-1.01a"; + compatible = "starfive,jh7110-axi-dma"; dma-coherent; reg = <0x0 0x16050000 0x0 0x10000>; clocks = <&clkgen JH7110_DMA1P_CLK_AXI>, @@ -639,13 +639,11 @@ resets = <&rstgen RSTN_U0_DW_DMA1P_AXI>, <&rstgen RSTN_U0_DW_DMA1P_AHB>, <&rstgen RSTN_U0_NOC_BUS_STG_AXI_N>; - reset-names = "rst_axi", "rst_ahb", "rst_stg"; interrupts = <73>; - #dma-cells = <2>; + #dma-cells = <1>; dma-channels = <4>; snps,dma-masters = <1>; snps,data-width = <3>; - snps,num-hs-if = <56>; snps,block-size = <65536 65536 65536 65536>; snps,priority = <0 1 2 3>; snps,axi-max-burst-len = <15>; @@ -966,6 +964,7 @@ jpu: jpu@11900000 { compatible = "starfive,jpu"; + dma-coherent; reg = <0x0 0x13090000 0x0 0x300>; interrupts = <14>; clocks = <&clkgen JH7110_CODAJ12_CLK_AXI>, @@ -984,6 +983,7 @@ vpu_dec: vpu_dec@130A0000 { compatible = "starfive,vdec"; + dma-coherent; reg = <0x0 0x130A0000 0x0 0x10000>; interrupts = <13>; clocks = <&clkgen JH7110_WAVE511_CLK_AXI>, @@ -1007,6 +1007,7 @@ vpu_enc: vpu_enc@130B0000 { compatible = "starfive,venc"; + dma-coherent; reg = <0x0 0x130B0000 0x0 0x10000>; interrupts = <15>; clocks = <&clkgen JH7110_WAVE420L_CLK_AXI>, @@ -1208,7 +1209,7 @@ <&rstgen RSTN_U0_TDM16SLOT_APB>, <&rstgen RSTN_U0_TDM16SLOT_TDM>; reset-names = "tdm_ahb", "tdm_apb", "tdm_rst"; - dmas = <&dma 20 1>, <&dma 21 1>; + dmas = <&dma 20>, <&dma 21>; dma-names = "rx","tx"; #sound-dai-cells = <0>; status = "disabled"; @@ -1242,7 +1243,7 @@ clock-names = "apb0", "pwmdac-apb", "pwmdac-core"; resets = <&rstgen RSTN_U0_PWMDAC_APB>; reset-names = "rst-apb"; - dmas = <&dma 22 1>; + dmas = <&dma 22>; dma-names = "tx"; #sound-dai-cells = <0>; status = "disabled"; @@ -1253,7 +1254,7 @@ reg = <0x0 0x100c0000 0x0 0x1000>; interrupt-names = "tx"; #sound-dai-cells = <0>; - dmas = <&dma 28 1>; + dmas = <&dma 28>; dma-names = "rx"; status = "disabled"; }; @@ -1293,7 +1294,7 @@ resets = <&rstgen RSTN_U0_I2SRX_3CH_APB>, <&rstgen RSTN_U0_I2SRX_3CH_BCLK>; reset-names = "rst_apb_rx", "rst_bclk_rx"; - dmas = <&dma 24 1>; + dmas = <&dma 24>; dma-names = "rx"; starfive,sys-syscon = <&sys_syscon 0x18 0x34>; #sound-dai-cells = <0>; @@ -1323,7 +1324,7 @@ "bclk-ext", "lrck-ext"; resets = <&rstgen RSTN_U0_I2SRX_3CH_APB>, <&rstgen RSTN_U0_I2SRX_3CH_BCLK>; - dmas = <&dma 24 1>; + dmas = <&dma 24>; dma-names = "rx"; starfive,sys-syscon = <&sys_syscon 0x18 0x34>; #sound-dai-cells = <0>; @@ -1348,7 +1349,7 @@ resets = <&rstgen RSTN_U0_I2STX_4CH_APB>, <&rstgen RSTN_U0_I2STX_4CH_BCLK>; reset-names = "rst_apb", "rst_bclk"; - dmas = <&dma 47 1>; + dmas = <&dma 47>; dma-names = "tx"; #sound-dai-cells = <0>; status = "disabled"; @@ -1377,7 +1378,7 @@ "mclk_ext", "bclk_ext", "lrck_ext"; resets = <&rstgen RSTN_U1_I2STX_4CH_APB>, <&rstgen RSTN_U1_I2STX_4CH_BCLK>; - dmas = <&dma 48 1>; + dmas = <&dma 48>; dma-names = "tx"; #sound-dai-cells = <0>; status = "disabled"; |