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authorSébastien Szymanski <sebastien.szymanski@armadeus.com>2019-10-22 16:16:55 +0300
committerShawn Guo <shawnguo@kernel.org>2019-10-28 09:48:55 +0300
commit7b45cc50cce7c28d24d7a97523500b29e9491b14 (patch)
treea27711b4b4a9bd02079b99931f5b61b411b06d43 /arch
parent9ce84cc667ae0efd2b4f48e97d63336b0f94b11d (diff)
downloadlinux-7b45cc50cce7c28d24d7a97523500b29e9491b14.tar.xz
ARM: dts: imx6qdl-apf6dev: use DRM bindings
Describe the parallel LCD using simple panel driver. Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/boot/dts/imx6qdl-apf6dev.dtsi50
1 files changed, 28 insertions, 22 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi b/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
index cf118c74111a..b8e74ab3c993 100644
--- a/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
@@ -21,33 +21,27 @@
disp0 {
compatible = "fsl,imx-parallel-display";
- interface-pix-fmt = "bgr666";
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ipu1_disp1>;
-
- display-timings {
- lw700 {
- clock-frequency = <33000033>;
- hactive = <800>;
- vactive = <480>;
- hback-porch = <96>;
- hfront-porch = <96>;
- vback-porch = <20>;
- vfront-porch = <21>;
- hsync-len = <64>;
- vsync-len = <4>;
- hsync-active = <1>;
- vsync-active = <1>;
- de-active = <1>;
- pixelclk-active = <1>;
- };
- };
+ pinctrl-0 = <&pinctrl_ipu1_disp0>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
- port {
display_in: endpoint {
remote-endpoint = <&ipu1_di0_disp0>;
};
};
+
+ port@1 {
+ reg = <1>;
+
+ display_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
};
gpio-keys {
@@ -76,6 +70,18 @@
};
};
+ panel {
+ compatible = "armadeus,st0700-adapt";
+ power-supply = <&reg_3p3v>;
+ backlight = <&backlight>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&display_out>;
+ };
+ };
+ };
+
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
@@ -351,7 +357,7 @@
>;
};
- pinctrl_ipu1_disp1: ipu1disp1grp {
+ pinctrl_ipu1_disp0: ipu1disp0grp {
fsl,pins = <
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100b1
MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x100b1