diff options
| author | Sandipan Das <sandipan.das@amd.com> | 2024-01-29 14:06:25 +0300 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2024-03-13 13:01:30 +0300 |
| commit | 29297ffffb0bf388778bd4b581a43cee6929ae65 (patch) | |
| tree | 23c10274b6ea6633d8da124dbf5cf814ba427666 /arch | |
| parent | b29f377119f68b942369a9366bdcb1fec82b2cda (diff) | |
| download | linux-29297ffffb0bf388778bd4b581a43cee6929ae65.tar.xz | |
perf/x86/amd/lbr: Discard erroneous branch entries
The Revision Guide for AMD Family 19h Model 10-1Fh processors declares
Erratum 1452 which states that non-branch entries may erroneously be
recorded in the Last Branch Record (LBR) stack with the valid and
spec bits set.
Such entries can be recognized by inspecting bit 61 of the corresponding
LastBranchStackToIp register. This bit is currently reserved but if found
to be set, the associated branch entry should be discarded.
Signed-off-by: Sandipan Das <sandipan.das@amd.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: https://bugzilla.kernel.org/attachment.cgi?id=305518
Link: https://lore.kernel.org/r/3ad2aa305f7396d41a40e3f054f740d464b16b7f.1706526029.git.sandipan.das@amd.com
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/x86/events/amd/lbr.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/x86/events/amd/lbr.c b/arch/x86/events/amd/lbr.c index eb31f850841a..4a1e600314d5 100644 --- a/arch/x86/events/amd/lbr.c +++ b/arch/x86/events/amd/lbr.c @@ -173,9 +173,11 @@ void amd_pmu_lbr_read(void) /* * Check if a branch has been logged; if valid = 0, spec = 0 - * then no branch was recorded + * then no branch was recorded; if reserved = 1 then an + * erroneous branch was recorded (see Erratum 1452) */ - if (!entry.to.split.valid && !entry.to.split.spec) + if ((!entry.to.split.valid && !entry.to.split.spec) || + entry.to.split.reserved) continue; perf_clear_branch_entry_bitfields(br + out); |