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| author | Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> | 2016-11-05 00:59:37 +0300 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2016-11-23 22:52:31 +0300 |
| commit | 28c43fbb3ca0a9a8f547aece94dac8d791358444 (patch) | |
| tree | 2b5fbcae41fb37ba3ee5276a7df25fefda4b0f35 /arch | |
| parent | bed98a59b62d3e121da2d8372425fd4e424b0aa6 (diff) | |
| download | linux-28c43fbb3ca0a9a8f547aece94dac8d791358444.tar.xz | |
ARM: dts: r8a7745: add IRQC support
Describe the IRQC interrupt controller in the R8A7745 device tree.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boot/dts/r8a7745.dtsi | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index 6fe48157f906..0b2e2f37150f 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -62,6 +62,25 @@ IRQ_TYPE_LEVEL_HIGH)>; }; + irqc: interrupt-controller@e61c0000 { + compatible = "renesas,irqc-r8a7745", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + }; + timer { compatible = "arm,armv7-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | |