diff options
| author | Anson Huang <Anson.Huang@nxp.com> | 2019-10-16 05:14:25 +0300 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2019-10-28 16:48:04 +0300 |
| commit | 03750c3796ccf19720ef49561b62b5bfda0cd397 (patch) | |
| tree | c9ad7af9deeefe93732cf698b0446f2efa4afeb7 /arch | |
| parent | e045f044e84ef9d500b4477f8e67875e5cb3fc21 (diff) | |
| download | linux-03750c3796ccf19720ef49561b62b5bfda0cd397.tar.xz | |
arm64: dts: imx8mm: Move usdhc clocks assignment to board DT
usdhc's clock rate is different according to different devices
connected, so clock rate assignment should be placed in board
DT according to different devices connected on each usdhc port.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 4 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mm.dtsi | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts index 5c3b23c4f91f..28ab17a277bb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts @@ -295,6 +295,8 @@ }; &usdhc2 { + assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; + assigned-clock-rates = <200000000>; pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; @@ -306,6 +308,8 @@ }; &usdhc3 { + assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; + assigned-clock-rates = <400000000>; pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc3>; pinctrl-1 = <&pinctrl_usdhc3_100mhz>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 7f4291aa36c6..93f2e620d70a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -702,8 +702,6 @@ <&clk IMX8MM_CLK_NAND_USDHC_BUS>, <&clk IMX8MM_CLK_USDHC1_ROOT>; clock-names = "ipg", "ahb", "per"; - assigned-clocks = <&clk IMX8MM_CLK_USDHC1>; - assigned-clock-rates = <400000000>; fsl,tuning-start-tap = <20>; fsl,tuning-step= <2>; bus-width = <4>; @@ -732,8 +730,6 @@ <&clk IMX8MM_CLK_NAND_USDHC_BUS>, <&clk IMX8MM_CLK_USDHC3_ROOT>; clock-names = "ipg", "ahb", "per"; - assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; - assigned-clock-rates = <400000000>; fsl,tuning-start-tap = <20>; fsl,tuning-step= <2>; bus-width = <4>; |