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authorVineet Gupta <vgupta@synopsys.com>2014-10-13 13:42:25 +0400
committerVineet Gupta <vgupta@synopsys.com>2015-06-19 15:39:34 +0300
commitfbfa26ae3b2001d0885938175f9af5a4c50a528c (patch)
treed98a145290cb48f8393bcc1888db747d86da07c0 /arch
parent11e14896ea3b0acbdcadb171bc40fc8fef37370e (diff)
downloadlinux-fbfa26ae3b2001d0885938175f9af5a4c50a528c.tar.xz
ARC: entry.S: common'ize scrtach reg freeup in intr + exceptions
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arc/include/asm/entry.h35
-rw-r--r--arch/arc/kernel/entry.S10
2 files changed, 18 insertions, 27 deletions
diff --git a/arch/arc/include/asm/entry.h b/arch/arc/include/asm/entry.h
index 884081099f80..9e844ab5eede 100644
--- a/arch/arc/include/asm/entry.h
+++ b/arch/arc/include/asm/entry.h
@@ -360,26 +360,26 @@
.endm
/*--------------------------------------------------------------
- * For early Exception Prologue, a core reg is temporarily needed to
+ * For early Exception/ISR Prologue, a core reg is temporarily needed to
* code the rest of prolog (stack switching). This is done by stashing
* it to memory (non-SMP case) or SCRATCH0 Aux Reg (SMP).
*
* Before saving the full regfile - this reg is restored back, only
* to be saved again on kernel mode stack, as part of pt_regs.
*-------------------------------------------------------------*/
-.macro EXCPN_PROLOG_FREEUP_REG reg
+.macro PROLOG_FREEUP_REG reg, mem
#ifdef CONFIG_SMP
sr \reg, [ARC_REG_SCRATCH_DATA0]
#else
- st \reg, [@ex_saved_reg1]
+ st \reg, [\mem]
#endif
.endm
-.macro EXCPN_PROLOG_RESTORE_REG reg
+.macro PROLOG_RESTORE_REG reg, mem
#ifdef CONFIG_SMP
lr \reg, [ARC_REG_SCRATCH_DATA0]
#else
- ld \reg, [@ex_saved_reg1]
+ ld \reg, [\mem]
#endif
.endm
@@ -393,7 +393,7 @@
.macro EXCEPTION_PROLOGUE
/* Need at least 1 reg to code the early exception prologue */
- EXCPN_PROLOG_FREEUP_REG r9
+ PROLOG_FREEUP_REG r9, @ex_saved_reg1
/* U/K mode at time of exception (stack not switched if already K) */
lr r9, [erstatus]
@@ -421,7 +421,7 @@
st r0, [sp, 4] /* orig_r0, needed only for sys calls */
/* Restore r9 used to code the early prologue */
- EXCPN_PROLOG_RESTORE_REG r9
+ PROLOG_RESTORE_REG r9, @ex_saved_reg1
SAVE_R0_TO_R12
PUSH gp
@@ -471,12 +471,8 @@
*-------------------------------------------------------------*/
.macro SAVE_ALL_INT1
- /* restore original r9 to be saved as part of reg-file */
-#ifdef CONFIG_SMP
- lr r9, [ARC_REG_SCRATCH_DATA0]
-#else
- ld r9, [@int1_saved_reg]
-#endif
+ /* restore original r9 */
+ PROLOG_RESTORE_REG r9, @int1_saved_reg
/* now we are ready to save the remaining context :) */
st event_IRQ1, [sp, 8] /* Dummy ECR */
@@ -496,12 +492,13 @@
.macro SAVE_ALL_INT2
- /* TODO-vineetg: SMP we can't use global nor can we use
- * SCRATCH0 as we do for int1 because while int1 is using
- * it, int2 can come
- */
- /* retsore original r9 , saved in sys_saved_r9 */
- ld r9, [@int2_saved_reg]
+ /*
+ * In SMP we can't use mem nor can we use SCRARCH_DATA0
+ * as we do for int1 because int2 can clobber it
+ * Hence 2 levels of intr are NOT allowed in SMP (by Kconfig)
+ */
+ /* restore original r9 */
+ PROLOG_RESTORE_REG r9, @int2_saved_reg
/* now we are ready to save the remaining context :) */
st event_IRQ2, [sp, 8] /* Dummy ECR */
diff --git a/arch/arc/kernel/entry.S b/arch/arc/kernel/entry.S
index d868289c5a26..13b14b8dcd8d 100644
--- a/arch/arc/kernel/entry.S
+++ b/arch/arc/kernel/entry.S
@@ -186,9 +186,8 @@ reserved: ; processor restart
; ---------------------------------------------
ENTRY(handle_interrupt_level2)
- ; TODO-vineetg for SMP this wont work
; free up r9 as scratchpad
- st r9, [@int2_saved_reg]
+ PROLOG_FREEUP_REG r9, @int2_saved_reg
;Which mode (user/kernel) was the system in when intr occured
lr r9, [status32_l2]
@@ -234,12 +233,7 @@ END(handle_interrupt_level2)
; ---------------------------------------------
ENTRY(handle_interrupt_level1)
- /* free up r9 as scratchpad */
-#ifdef CONFIG_SMP
- sr r9, [ARC_REG_SCRATCH_DATA0]
-#else
- st r9, [@int1_saved_reg]
-#endif
+ PROLOG_FREEUP_REG r9, @int1_saved_reg
;Which mode (user/kernel) was the system in when intr occured
lr r9, [status32_l1]