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authorMiquel Raynal <miquel.raynal@bootlin.com>2019-01-08 19:24:38 +0300
committerGregory CLEMENT <gregory.clement@bootlin.com>2019-02-08 23:58:59 +0300
commitc38e13a2f8162a6d92985908c4a760a23c044dfe (patch)
treebb81b826088380daae06d278f0d4ec9757f7f91c /arch
parent2ef303f0fe44feee4a3ca8bd62fca86c105927d2 (diff)
downloadlinux-c38e13a2f8162a6d92985908c4a760a23c044dfe.tar.xz
arm64: dts: marvell: armada-3720-espressobin: declare PCIe PHY
The PCIe node is wired to the second PHY of the COMPHY IP. Suggested-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
index 67fa84bf8686..d17fd5600c55 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
@@ -46,6 +46,7 @@
/* J9 */
&pcie0 {
status = "okay";
+ phys = <&comphy1 0>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
};