diff options
| author | Horatiu Vultur <horatiu.vultur@microchip.com> | 2022-09-12 22:26:29 +0300 |
|---|---|---|
| committer | Claudiu Beznea <claudiu.beznea@microchip.com> | 2022-09-13 10:14:24 +0300 |
| commit | f5fc22cbbdcd349402faaddf1a07eb8403658ae8 (patch) | |
| tree | d5f33352bf117205699d37bd8250b9bc06408e49 /arch | |
| parent | 3d074b750d2b4c91962f10ea1df1c289ce0d3ce8 (diff) | |
| download | linux-f5fc22cbbdcd349402faaddf1a07eb8403658ae8.tar.xz | |
ARM: dts: lan966x: Fix the interrupt number for internal PHYs
According to the datasheet the interrupts for internal PHYs are
80 and 81.
Fixes: 6ad69e07def67c ("ARM: dts: lan966x: add MIIM nodes")
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220912192629.461452-1-horatiu.vultur@microchip.com
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boot/dts/lan966x.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi index 894bf9da19a4..0bf818713422 100644 --- a/arch/arm/boot/dts/lan966x.dtsi +++ b/arch/arm/boot/dts/lan966x.dtsi @@ -541,13 +541,13 @@ phy0: ethernet-phy@1 { reg = <1>; - interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; phy1: ethernet-phy@2 { reg = <2>; - interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; }; |