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| author | Hanjun Guo <hanjun.guo@linaro.org> | 2019-03-05 16:40:58 +0300 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2019-03-19 17:55:10 +0300 |
| commit | 0ecc471a2cb7d4d386089445a727f47b59dc9b6e (patch) | |
| tree | edda8a42707c96a82cc21b4d2ff06b7e622abae9 /arch | |
| parent | efd00c722ca855745fcc35a7e6675b5a782a3fc8 (diff) | |
| download | linux-0ecc471a2cb7d4d386089445a727f47b59dc9b6e.tar.xz | |
arm64: kpti: Whitelist HiSilicon Taishan v110 CPUs
HiSilicon Taishan v110 CPUs didn't implement CSV3 field of the
ID_AA64PFR0_EL1 and are not susceptible to Meltdown, so whitelist
the MIDR in kpti_safe_list[] table.
Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
Reviewed-by: John Garry <john.garry@huawei.com>
Reviewed-by: Zhangshaokun <zhangshaokun@hisilicon.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/kernel/cpufeature.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index e24e94d28767..4061de10cea6 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -963,6 +963,7 @@ static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), + MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), { /* sentinel */ } }; char const *str = "command line option"; |