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| author | Windsome Zeng <windsome.zeng@starfivetech.com> | 2024-01-11 13:29:10 +0300 |
|---|---|---|
| committer | Windsome Zeng <windsome.zeng@starfivetech.com> | 2024-01-11 13:29:10 +0300 |
| commit | e729b64bb83be8fc0d03f81673278f2d78fa4748 (patch) | |
| tree | 0998b48718291357dc95314bf19a80e138935e70 /arch | |
| parent | fa86f41550a08f2c087b488fdedba4f64e0a3d16 (diff) | |
| download | linux-e729b64bb83be8fc0d03f81673278f2d78fa4748.tar.xz | |
riscv: cpu: cache: Implement a new method to flush the entire L2 cache
According to the manual of SiFive U74, implement a new method to flush the entire L2 cache by using the Zero Device.
After testing, 512KB is the critical point between the old and new way. It's better to use sifive_ccache_flush_entire
function while data size is larger than cache size. Or it will improve more at 512KB when you know what you are doing.
Signed-off-by: Windsome Zeng <windsome.zeng@starfivetech.com>
Diffstat (limited to 'arch')
| -rwxr-xr-x | arch/riscv/boot/dts/starfive/jh7110.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 19928efe3b1a..845d34aa373c 100755 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -281,7 +281,7 @@ cachectrl: cache-controller@2010000 { compatible = "sifive,fu740-c000-ccache", "cache"; - reg = <0x0 0x2010000 0x0 0x4000 0x0 0x8000000 0x0 0x2000000>; + reg = <0x0 0x2010000 0x0 0x4000 0x0 0x8000000 0x0 0x2000000 0x0 0xa000000 0x0 0x2000000>; reg-names = "control", "sideband"; interrupts = <1 3 4 2>; cache-block-size = <64>; |