diff options
| author | ziv.xu <ziv.xu@starfive.com> | 2023-04-04 10:28:18 +0300 |
|---|---|---|
| committer | ziv.xu <ziv.xu@starfive.com> | 2023-04-19 11:59:27 +0300 |
| commit | 7eb7082a3cbd0e7f83e2feaeb77feb1ef7d17fa0 (patch) | |
| tree | 3ca4ac720b7b689ba4a0d3801afd413a99d77f48 /arch | |
| parent | 9c3d82fe9bab57d1e4dbd044d52796d665a6008b (diff) | |
| download | linux-7eb7082a3cbd0e7f83e2feaeb77feb1ef7d17fa0.tar.xz | |
spi-cadence-quadspi:modify frequency limit and set the parent of qspi ref clk
modify frequency limit and set the parent of qspi ref clk
Signed-off-by: ziv.xu <ziv.xu@starfive.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/riscv/boot/dts/starfive/jh7110.dtsi | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 9939e23db60d..bc2b660e1096 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -342,11 +342,13 @@ clocks = <&clkgen JH7110_QSPI_CLK_REF>, <&clkgen JH7110_QSPI_CLK_APB>, <&clkgen JH7110_AHB1>, - <&clkgen JH7110_QSPI_CLK_AHB>; + <&clkgen JH7110_QSPI_CLK_AHB>, + <&clkgen JH7110_QSPI_REF_SRC>; clock-names = "clk_ref", "clk_apb", "ahb1", - "clk_ahb"; + "clk_ahb", + "clk_src"; resets = <&rstgen RSTN_U0_CDNS_QSPI_APB>, <&rstgen RSTN_U0_CDNS_QSPI_AHB>, <&rstgen RSTN_U0_CDNS_QSPI_REF>; |